A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm

Abstract

A dual-slope PFD (phase-frequency detector)/CP (charge pump) frequency synthesizer architecture for reducing the settling time of the loop is presented in the paper, which can achieve automatic adjustment of the loop bandwidth and high spectral purity. An adaptive self-tuning algorithm is introduced to effectively enlarge the frequency tuning range in a low VCO gain, where the aim of the adaptive control is for fast convergence to a proper control word. The on-chip VCO achieves a low phase noise by utilizing a tail-current filter technique and a differential inductor, and a 3-4GHz tuning range by a switched capacitor array. Based on 0.18mum 1.8V CMOS technology, simulation shows that the frequency synthesizer has a <15mus settling time, and the phase noise is lower than -121Bc@ 1MHz.