Spread Spectrum Clock Research Articles

A Highly Linear, AEC-Q100 Compliant Signal Conditioning IC for Automotive Piezo-Resistive Pressure Sensors

In this paper, the design of a signal conditioning analog front-end (AFE) IC for an automotive piezo-resistive type pressure sensor is presented. To improve the pressure-sensing accuracy and compensate for variations in the pressure sensor and signal conditioning IC, gauge factor calibration, digital automatic offset, and gain calibration are proposed and implemented with low power consumption. By using a high-resolution analog-to-digital converter and digital-to-analog converter, the digital automatic calibration circuit can guarantee linearity of output voltage with respect to pressure to within 0.5%. As the analog signal is converted to a digital signal, accuracy in the AFE IC improves. To improve the reliability in the automotive environment, over-voltage and reverse-voltage protection circuits are integrated with the electrostatic discharge protection circuit. Also, electromagnetic interference is reduced by using the proposed spread spectrum clock generator. The proposed design is implemented using 2P4M 0.35 μm CMOS technology with an active area of 1.94 mm × 1.94 mm. Full output ranges from 0.5 to 4.5 V. The ratiometricity error is within ±0.25% when the supply voltage is changed by ±10%. Current consumption is 4.7 mA from a 5 V supply. The output accuracy is within ±0.5% with respect to the PVT variations.

Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

This study presents a spread spectrum clock generator (SSCG) circuit for high-speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage-controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum-spreading profile. The control unit consists of an analogue charge pump-based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high-speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.

A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation

This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio ( ${\delta }$ ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a −104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

A Design of a 92.4% Efficiency Triple Mode Control DC–DC Buck Converter With Low Power Retention Mode and Adaptive Zero Current Detector for IoT/Wearable Applications

This paper presents a retention/ pulse frequency modulation (PFM)/ pulse width modulation (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed dc–dc buck converter is capable of handling loads from 10 μA to 20 mA with high efficiency by applying triple mode (retention mode, PFM mode, and PWM mode), gate split technique, and AZCD. Retention mode is proposed to extend wide load range at ultralight load. Gate split technique adjusts the conduction loss and switching loss. AZCD reduces the operation duty of the high-speed comparator and avoid reverse current below light load. In IoT applications, each node communicates with other nodes through a Bluetooth low energy transceiver, which consumes very low current and is highly sensitive to supply noise. Therefore, the proposed dc–dc buck converter adopts the SSCG technique to reduce electromagnetic interference by up to 18 dB. This chip is implemented using 0.13 μm CMOS technology with an active area of $\text{820}\times \text{800}\;\mu \text{m}^{2}$ . The maximum power efficiency of the proposed dc–dc buck converter is 92.4% at a switching frequency of 2.5 MHz when the load current range is 10 to 20 mA. The input voltage range and the regulated output voltage are 2.2–3.3 and 1.7 V, respectively. In addition, the proposed dc–dc buck converter achieves over 74.2% efficiency in retention mode when the load current range is from 10 to 500 μA.

Study on LLC Resonant Converter for EMI Reduction

The problem of EMI reduction is the topic of major interest in recent years. EMI reduction is one of the aspects in the power converter operation and control. EMI Reduction refers to techniques such as spread spectrum clocking to reduce the effects of electromagnetic interference or EMI,EMI is defined as EMI = kIAf2 where I is the current, A is the loop area, f is the frequency, and k is the constant depending on PCB materials and other factors. Among various dc/dc converters, LLC resonant converter has been attracting more and more attention for its inherent merits, like soft switching, low EMI, high efficiency, and high power density. In this paper how EMI can be reduced by using LLC resonant converter and their modeling and designing methodologies presented.

A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications

ABSTRACTIn this letter, a 6‐GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18‐pm CMOS technology is presented. The 3rd‐order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second‐order delta‐sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30‐MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:622–624, 2017

A spread-spectrum clock generator with direct VCO modulation in open-loop

A spread-spectrum clock generator with direct VCO modulation in open-loop

확산 스펙트럼 생성기를 이용한 적외선 카메라의 방사노이즈 저감에 관한 연구

적외선 카메라는 Mil-Std-461 항목 중 복사성 방사 잡음 시험, RE-102의 규격 만족에 어려움을 겪는다. 특히 무인항공기용 전자장비의 경우 차폐 케이블을 사용하지 않아 전자기적합성 규격 만족이 어려워 적절한 대응 설계가 필요하다. 무인정찰기용 적외선 카메라의 RE-102 시험 중 50~200 MHz 대역에서 30 dBuV/m 이상 규격을 초과하는 방사 잡음을 확인하였다. Pcb em scan 결과, 디지털 제어 신호 클록의 체배 주파수에 의한 첨두 잡음 발생을 확인하였고, 카메라의 제어 클록에 3 % 다운 스프레딩 방식의 확산 스펙트럼 클록 생성기를 적용하여 방사 잡음이 최대 22.9 dBuV/m 감소함을 확인하였다. The infrared camera is difficult to satisfy the RE-102 specification of Mil-Std-461. Especially, in the case of UAV electronics, shielded cable is not used, so it is difficult to meet the electromagnetic compatibility standard. In the RE-102 test of the IR camera for UAV, radiated noise exceeding 30 dBuV/m was observed in the range of 50 MHz to 200 MHz. As a result of pcb em scan, peak noise which caused by the harmonic frequency of the digital control signal clock was observed. Radiated noise was reduced by up to 22.9 dBuV/m by applying the spread spectrum clock generator(SSCG) with 3 % down spreading method to the camera control clock.

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.

Practical considerations for electromagnetic interference suppression rate with spread spectrum clocking

Electromagnetic interference (EMI) is one of the critical design issues affecting the performance of consumer electronic devices, especially for wireless devices and applications. EMI can easily degrade the performance of systems through undesirable spectral components and by interference from the system itself. Therefore, there are a lot of techniques addressing this issue such as differential signaling, shielding, and spread spectrum clocking (SSC). Specifically, SSC is getting more attention since it directly addresses EMI issues at its source. In this paper, SSC generation and its EMI suppression rate are discussed, and two practical considerations are introduced to improve the measurement accuracy.

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C

First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from $-40^{\circ}{\hbox {C}}$ to 170 $^{\circ}{\hbox {C}}$ as demanded strongly in automotive uses. Much attention has been paid to the degradation of the reliability characteristics along with the process shrinkage. Temperature-adjusted word-line overdrive scheme improves random read access frequency by 15% and realizes both of 6.4 GB/s read throughput by 200 MHz no-wait random access of code flash macros and more than ten times longer TDDB lifetime of WL drivers. Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million rewrite cycles. Source-side injection (SSI) program with negative back-bias voltage achieves 63% reduction of program pulse time and, consequently, realizes 2.0 MB/s write throughput of code flash macros. A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and peak power of EMI noise is reduced by 19 dB.

A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

This paper presents a fractional-N phase-locked loop based spread spectrum clock generator (SSCG) using a programmable linear frequency modulator. The SSCG provides a programmable frequency deviation and modulation frequency regardless of its operating frequency. The ranges of frequency-deviation ratio and modulation frequency are 0–80% and 0–100 kHz with 610 Hz step resolution. The proposed SSCG successfully support five serial-link standards by using a single SSCG, and can be applied to various switching circuits such as class-D power amplifiers or switching power converters. The EMI reduction was measured to be 10.24–13.94 dB under 100-kHz resolution bandwidth. The proposed SSCG was fabricated using a 0.13-μm CMOS process with an active area of 0.11 mm2, while consuming an overall power of 6.28 mW at 1 GHz.

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS

Spread-spectrum clocking is an established approach to mitigate electromagnetic interference (EMI) of digital circuits, by intentionally sweeping the clock frequency. In this way, the energy of each clock harmonic is spread over a larger bandwidth, thereby reducing the peak of the interfering spectrum. This paper describes an highly flexible all-digital spread-spectrum clock generator (SSCG) realized with a standard-cells design flow. The developed circuit supports discontinuous frequency modulation profiles (with improved EMI reduction capability) and features reduced output jitter, due to delay interpolators and digital compensation of delay path asymmetries. The proposed SSCG is ideally suited for complex system on chips applications, having programmable spreading parameters, frequency synthesis capability and reduced recovery time to support local standby modes. The SSCG is implemented in bulk 28 nm CMOS technology, presents a maximum working frequency of 3.3 GHz and less than 3.2 ps $_{\rm rms}$ output jitter. The measured peak level reduction of the clock power spectrum, at 1.0 GHz output frequency, is 27.0 dB with a 10% modulation depth. The power dissipation is 29.3 mW @ 3.3 GHz and the area occupation is 0.031 mm.

Delta-Sigma Digital-to-Time Converter for Band-Select Spread Spectrum Clock

This paper proposes an innovative method of converting digital signal to time-domain analog signal, which fully enjoys robustness and digital circuit friendliness. This technique utilizes a digital delta-sigma ( ) modulator following a digital-to-time converter (DTC) circuit with various modulation methods. As an application of the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as for DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noisespectrum spread in AM, FM radio bands. The proposed circuit takes advantage of digital technology, which is simple, fast (reachable at high clock frequency) and flexible (programmable).

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

In this brief, a low-cost low-power all-digital spread-spectrum clock generator (ADSSCG) is presented. The proposed ADSSCG can provide an accurate programmable spreading ratio with process, voltage, and temperature variations. To maintain the frequency stability while performing triangular modulation, the fast-relocked mechanism is proposed. The proposed fast-relocked ADSSCG is implemented in a standard performance 90-nm CMOS process, and the active area is $200~\mu $ m $\times 200~\mu $ m. The experimental results show that the electromagnetic interference reduction is 14.61 dB with a 0.5% spreading ratio and 19.69 dB with a 2% spreading ratio at 270 MHz. The power consumption is $443~\mu $ W at 270 MHz with a 1.0 V power supply.

Spur Reduction Techniques With a Switched-Capacitor Feedback Differential PLL and a DLL-Based SSCG in UHF RFID Transmitter

This paper presents a robust spur reduction technique using a switched-capacitor feedback differential phase-locked loop (PLL) and a delay-locked-loop (DLL)-based spread-spectrum clock generation in a UHF-band RF identification transmitter (TX). The proposed differential PLL is characterized by adopting a switched-capacitor common-mode feedback and distributed varactor biasing scheme to the differential charge pump and voltage-controlled oscillator designs, respectively, which results in down to ${-}{\hbox{94}}$ dBc in reference spur rejection with all digital parts off. Additionally, by adopting an 8-bit DLL and Hershey-Kiss modulated profile together, the proposed spread-spectrum clock generator shows more than 20-dB electromagnetic-interference reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18- $\mu{\hbox{m}}$ CMOS process, the proposed TX achieves ${ -dBc spur suppression with 25-dBm transmit power at 920 MHz, which complies with the most stringent regulatory spectral mask without a surface acoustic wave filter.

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.

High accuracy, Low Power Spread Spectrum Clock Generator to Reduce EMI for Automotive Applications

This paper presents a Spread Spectrum Clock Generator (SSCG) based on Relaxation oscillator using Up/Down Counter. The current is controlled by a counter and the spread spectrum of the Relaxation Oscillator. A Relaxation Oscillator with temperature compensation using the BGR and ADC is presented. The current to determine the frequency of the Relaxation Oscillator can be controlled. The output frequency of the temperature can be compensated by adjusting the current according to the temperature using the code that is the output from the ADC and BGR. EMI Reduction of SSCG is 11 dB, and Spread down frequency is 150 kHz. The current consumption is <TEX>$600{\mu}A$</TEX> from 5V and the operating frequency is from 2.3 MHz to 5.75 MHz. The rate of change of the output frequency with temperature was approximately <TEX>${\pm}1%$</TEX>. The SSCG is fabricated in a 0.35um CMOS process with active area <TEX>$250um{\times}440um$</TEX>.

Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator

A phase-rotator-based all-digital phase-locked loop for spread-spectrum clock generation is presented. It combines a dual-tone triangular and a random modulation profile to achieve a balance between electromagnetic interference reduction and broadband jitter generation. The test chip, fabricated using a 90-nm CMOS process, achieves a 43-dB total EMI reduction at the resolution bandwidth of 100 Hz without incurring a notable bit-error-rate penalty at the receiver's side and consuming only 15.8 mW at 6 GHz from a 1-V supply.

Short-term Optimized Spread Spectrum Clock Generator for EMI Reduction in Switching DC/DC Converters

We present here a prototype of a Spread Spectrum Clock Generator designed for switching DC/DC converters, which has been optimized in accordance to EMC international regulations to improve EMI reduction with respect to standard approaches. Such an optimization has been obtained trough the theoretical computation of the power spectrum as measured by a spectrum analyzer when a chaotic or random-like PAM modulating signal is employed. To experimentally validate the achieved theoretical results, the circuit has been fabricated in CMOS 0.18 μm technology, and embeds two simple and effective modulators, the first one relying on a full analog hardware, the second one on a simple digital core. Measurements on a DC/DC converter in accordance with EMC regulations confirm that the prototype can achieve a 7 dB EMI reduction improvement with respect to classical solutions based on out of audible triangular waveforms.