Spin Transfer Torque Magnetic Tunnel Junction Research Articles

A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions

Two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions (STT-MTJs) is proposed that is smaller than the conventional ones with equivalent performance. The power supply voltage dependence of the area for the two-NFET bootstrap type selective device that can switch MTJs within 10 ns is compared with those of the conventional single-NFET, single-PFET, and CMOS type selective devices with the same performance in 90 nm technology node. It is found that the two-NFET bootstrap type selective device can be smaller than the conventional ones especially for the power supply voltage equal to or lower than 0.9 V. The two-NFET bootstrap type selective device is shown to maintain scalability to 32 nm node just like the CMOS one, while the conventional single-NFET and single-PFET selective devices fail to be scaled properly. This selective device can be applied to every high-performance MOS/MTJ hybrid circuit for increasing the integration density.

2T–1R STT-MRAM memory cells for enhanced on/off current ratio

Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell topologies are introduced to improve both the sense margin and the current ratio observed by the sense circuitry. These circuits utilize an additional transistor per cell in either a diode connected or gate connected manner and maintain leakage current immunity within the data array. An order of magnitude increase in the current ratio over a traditional 1T–1R structure is observed. This improvement comes at a cost of 61% and 117% increase in area, respectively, for the diode and gate connected cells.

Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor Δ. The IMP error probability decreases exponentially with increasing TMR and Δ.

A Novel Verilog-A model of Spin Torque Transfer Magnetic Tunnel Junction

A novel simple and efficient model of Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) using Verilog-A is presented. The model accurately emulates the main properties of an STT-MTJ which includes Tunnel Magneto Resistance Ratio (TMR), its dependence on the voltage bias and the critical switching current. The novelty of the model lies in the fact that the voltage dependence of TMR has been modeled using a single equation. The model can be used for faster simulations of hybrid Magnetic CMOS circuits and in various other wide range of applications. The model was developed in Verilog-A and verified using Synopsys Hspice 2010.

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Transfer Torque-Magnetic Tunneling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated and compared by implementing a 16-bit carry look-ahead adder and a 32-bit Wallace tree multiplier in STLA and FPGA.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks.

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

Probabilistically Programmed STT-MRAM

Novel memory programming methods and corresponding memory structures are presented in this paper. Unlike conventional memory programming, this programming technique does not require deterministic switching of memory elements. This technique explicitly exploits the probabilistic switching characteristics of memory elements such as spin-transfer torque magnetic tunnel junction (STT-MTJ) to reduce programming power and delay. This technique also allows multilevel cell (MLC) spin-transfer torque magnetoresistive random access memory (STT-MRAM) to be fabricated with existing STT-MTJ fabrication processes, thus making high capacity STT-MRAM chips readily achievable. The optimal STT-MTJ switching probabilities are given in this paper for reaching minimum programming delay, power, and iteration. Moreover, this paper proves, by applying probabilistic programming to existing STT-MTJs, both programming delay and power can be reduced to levels beyond the reach of conventional deterministic programming. Furthermore arbitrarily small programming bit error rate (BER) can be accomplished in theory using probabilistic programming without much penalty on average programming delay and power. On the contrary, deterministic programming always presents finite programming BER, which is expensive to reduce in terms of programming power and delay. The MLC capability of STT-MTJ clusters has also been confirmed using fabricated STT-MTJ devices. The major circuitries for implementing probabilistically programmed MLC STT-MRAM are also presented in this paper.

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

ABSTRACTWe proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power-gating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity.

Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances

High leakage power in sub-100-nm memory technology nodes drives the need for nonvolatile memory devices to reduce power consumption and enhance battery life. Spin-transfer torque magnetic tunneling junction (STT-MTJ) is a promising nonvolatile memory device with comparable read and write performances as SRAM and eDRAM with almost zero standby power. In this paper, we present a simulation framework that can solve transport [using nonequilibrium Green's function (NEGF) formalism] and magnet dynamics [using Landau-Lifshitz-Gilbert (LLG) equation] self-consistently to study the read and write performances of STT-MTJ. Due to process variations, thermal disturbances, and stray fields, the performance of STT-MTJ degrades and results in one transistor-one STT-MTJ (IT-ISTTMTJ) memory failures. A thorough memory design space investigation can help us to reduce such failures. Hence, we present a design space exploration framework for IT-ISTTMTJ memory, which consists of magnetic materials with different RAPA products, different genres of MTJ stacks, and a transistor. A comprehensive study based on critical memory performance metrics such as tunneling magnetoresistance, JC, and write cycle shows the relative merits and demerits of each MTJ stack for embedded memory applications. Finally, the benefits of synthetic antiferromagnet free layer in providing immunity against stray fields are shown illustrating the need for coupled free-layer stacks in scaled technology nodes.

Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.