Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Abstract

We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.