Spin-transfer Torque RAM Research Articles

Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM

Spin-transfer-torque RAM (STT-RAM) is one of the emerging nonvolatile memories for last-level cache (LLC) featuring high density and low leakage. However, long latency for the write operation, which comes from the characteristics of nonvolatility, degrades performance when STT-RAM is employed as LLC. To overcome this problem, we revisit the existing cache update policy and propose a new cache update policy to exploit the asymmetric write characteristics of STT-RAM. In our proposal, the data are written into a fast writeable block, regardless of the original position when the block arrives at the LLC. This paper proves the efficiency of our update policy based on analytical models and gives detailed information for implementing the policy. The experimental results show our scheme reduces slow writes by 77.6%, which leads a 31.1% reduction in write latency.

Dual referenced composite free layer design optimization for improving switching efficiency of spin-transfer torque RAM

We present a detailed numerical analysis of switching efficiency for the recently proposed dual referenced composite free layer structure with respect to Gilbert damping. Low anisotropy assistive layers enable reduction of Gilbert damping and an increase of partial spin polarization within those low anisotropy layers—not feasible with single layer structures that require high anisotropy for thermal stability. When the damping of the soft layers is ultra-low, an efficiency (kBT/μA) of 8.1 is achieved for the composite structure with perpendicular anisotropy. This represents an improvement of 286% and 913% relative to the state-of-the-art dual-referenced and conventional STT-RAM cells, respectively. Results for structures with longitudinal anisotropy are also presented. A linear calculation of the STT polarization pre-factor is also described that captures all reflections.

Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing

ABSTRACTFog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact and demonstrates that ECCs shorten the lifetime of STT-RAM cache lines by more than 50 percent due to ECCs high write activity. Then, we propose the Floating-ECC architecture for increasing the lifetime of the STT-RAM caches. The main idea is to evenly distribute the ECC write activity over all bits of cache lines by periodically relocating the ECC bits inside the cache lines. The simulation results for the most conventional ECC scheme, i.e., interleaved Single Error Correction-Double Error Detection (SEC-DED), show that Floating-ECC increases the lifetime of L2 and L3 caches by more than 318 percent and 254 percent, respectively.

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

The breakdown of Dennard scaling prevents us from powering all transistors simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work on power-efficient core and memory architecture designs. However, the research for addressing dark silicon challenges with network-on-chip (NoC), which is a major contributor to the total chip power consumption, is largely unexplored. In this paper, we comprehensively examine the network power consumers and the drawbacks of the conventional power-gating techniques. To overcome the dark silicon issue from the NoC's perspective, we propose DimNoC, a dim silicon scheme, which leverages recent drowsy SRAM design and spin-transfer torque RAM (STT-RAM) technology to replace pure SRAM-based NoC buffers. In particular, we propose two novel hybrid buffer architectures: 1) a hierarchical buffer architecture, which divides the input buffers into a set of levels with different power states and 2) a banked buffer architecture, which organizes the drowsy SRAM and the STT-RAM in different banks, and accesses them in an interleaved fashion to hide the long write latency of STT-RAM. In addition, our hybrid buffer design enables NoC data retention mechanism by storing packets in drowsy SRAM and nonvolatile STT-RAM in a lossless manner. Combined with flow control schemes, the NoC data retention mechanism can improve network performance and power simultaneously. Our experiments over real workloads show that DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product reduction, and 7.6% router area reduction compared with pure SRAM-based NoC design.

Retention Testing Methodology for STTRAM

Spin-torque transfer RAM (STTRAM) is a promising memory technology due to its low power, high speed, and robustness. However, the shift of retention time from a few years to a few microseconds due to temperature, thermal, statistical, and stochastic variations makes retention testing nontrivial and time consuming. This article analyzes the impact of process variation, temperature, and disturb current on data retention. It provides a design-for-test (DFT) solution to reduce the test time by incorporating a weak write test mode to effectively screen the weak bits from other strong bits. Additionally, it presents an at-burn-in technique and an after-burn-in technique to test data retention. These techniques compress the retention time test to the order of microseconds.

Guest Editorial Emerging Memories—Technology, Architecture and Applications (Second Issue)

Since CMOS technology is approaching the end of scaling roadmap, there is a need to explore alternative technologies to assist or replace CMOS technology. Furthermore, the growth in new application areas such as data analytics, Internet-of-Things (IoT), cognitive computing, cloud computing and fog computing requires new features that are not readily available in CMOS technology. Emerging memories can potentially solve the scalability issues and cater to the new applications by providing features such as non-volatility and resistive computation. The properties of emerging memory technologies such as Spin Transfer Torque RAM (STTRAM) and Resistive RAM (ReRAM) can also be altered by changing the materials, shape and design. Therefore, these memories could be customized to suit target application or make trade-off between various design parameters such as density, latency, power and performance. For designing meaningful circuits and systems using emerging memories, it is also important to identify their limitations and solve those using appropriate techniques. This special issue covers the opportunities presented by the emerging memory technologies across the design hierarchy and their associated challenges. It introduces alternate structures, technologies and methodologies to mitigate the limitations of emerging memories. Circuit, architecture and applications built around the emerging memory technologies are also provided.

Reducing Synchronization Cost for Single-Level Store in Mobile Systems

Emerging byte-addressable non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.

LAP

Emerging non-volatile memory (NVM) technologies, such as spin-transfer torque RAM (STT-RAM), are attractive options for replacing or augmenting SRAM in implementing last-level caches (LLCs). However, the asymmetric read/write energy and latency associated with NVM introduces new challenges in designing caches where, in contrast to SRAM, dynamic energy from write operations can be responsible for a larger fraction of total cache energy than leakage. These properties lead to the fact that no single traditional inclusion policy being dominant in terms of LLC energy consumption for asymmetric LLCs. We propose a novel selective inclusion policy, Loop-block-Aware Policy ( LAP ), to reduce energy consumption in LLCs with asymmetric read/write properties. In order to eliminate redundant writes to the LLC, LAP incorporates advantages from both non-inclusive and exclusive designs to selectively cache only part of upper-level data in the LLC. Results show that LAP outperforms other variants of selective inclusion policies and consumes 20% and 12% less energy than non-inclusive and exclusive STT-RAM-based LLCs, respectively. We extend LAP to a system with SRAM/STT-RAM hybrid LLCs to achieve energy-efficient data placement, reducing the energy consumption by 22% and 15% over non-inclusion and exclusion on average, with average-case performance improvements, small worst-case performance loss, and minimal hardware overheads.

LER: Least-Error-Rate Replacement Algorithm for Emerging STT-RAM Caches

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation. This is done by comparing the contents of the incoming block with lines in a cache set. Compared with Least Recently Used (LRU) algorithm, LER reduces the error rate by 2× with about 1.4% and 3.6% performance and dynamic energy consumption overheads, respectively. Moreover, LER imposes no area overhead to system.

Guest Editorial Emerging Memories—Technology, Architecture and Applications (First Issue)

Since CMOS technology is approaching the end of scaling roadmap, there is a need to explore alternative technologies to assist or replace CMOS technology. Furthermore, the growth in new application areas such as data analytics, Internet-of-Things (IoT), cognitive computing, cloud computing and fog computing requires new features that are not readily available in CMOS technology. Emerging memories can potentially solve the scalability issues and cater to the new applications by providing features such as non-volatility and resistive computation. The properties of emerging memory technologies such as Spin Transfer Torque RAM (STTRAM) and Resistive RAM (ReRAM) can also be altered by changing the materials, shape and design. Therefore, these memories could be customized to suit target application or make trade-off between various design parameters such as density, latency, power and performance. For designing meaningful circuits and systems using emerging memories, it is also important to identify their limitations and solve those using appropriate techniques. This special issue covers the opportunities presented by the emerging memory technologies across the design hierarchy and their associated challenges. It introduces alternate structures, technologies and methodologies to mitigate the limitations of emerging memories. Circuit, architecture and applications built around the emerging memory technologies are also provided.

A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems

Non-volatile memory (NVM) devices, such as Flash, phase change RAM, spin transfer torque RAM, and resistive RAM, offer several advantages and challenges when compared to conventional memory technologies, such as DRAM and magnetic hard disk drives (HDDs). In this paper, we present a survey of software techniques that have been proposed to exploit the advantages and mitigate the disadvantages of NVMs when used for designing memory systems, and, in particular, secondary storage (e.g., solid state drive) and main memory. We classify these software techniques along several dimensions to highlight their similarities and differences. Given that NVMs are growing in popularity, we believe that this survey will motivate further research in the field of software technology for NVMs.

Sequoia: A High-Endurance NVM-Based Cache Architecture

Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure $10^{9}$ – $10^{12}$ writes per cell, making a nonvolatile cache (NV-cache) with a lifetime of dozens of years under ideal working conditions. However, nonuniformity in writes to different cache lines considerably reduces the NV-cache lifetime to a few months. Writes to cache lines can be made uniformly by wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with negligible performance overhead of $13\times $ for different cache configurations.

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density alternative to SRAM for large on-chip caches. However, its high write energy has been considered as a serious drawback. Hybrid caches mitigate this problem by incorporating a small SRAM cache for write-intensive data along with an STT-RAM cache. In such architectures, choosing cache blocks to be placed into the SRAM cache is the key to their energy efficiency. This paper proposes a new hybrid cache architecture called prediction hybrid cache. The key idea is to predict write intensity of cache blocks at the time of cache misses and determine block placement based on the prediction. We design a write intensity predictor that realize the idea by exploiting a correlation between write intensity of blocks and memory access instructions that incur cache misses of those blocks. It includes a mechanism to dynamically adapt the predictor to application characteristics. We also design a hybrid cache architecture in which write-intensive blocks identified by the predictor are placed into the SRAM region. Evaluations show that our scheme reduces energy consumption of hybrid caches by 28 percent (31 percent) on average compared to the existing hybrid cache architecture in a single-core (quad-core) system.

Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory

The increasing adoption of graphics processing units (GPUs) for high-performance computing raises the reliability challenge, which is generally ignored in traditional GPUs. GPUs usually support thousands of parallel threads and require a sizable register file. Such large register file is highly susceptible to soft errors and power-hungry. Although ECC has been adopted to register file in modern GPUs, it causes considerable power overhead, which further increases the power stress. Thus, an energy-efficient soft-error protection mechanism is more desirable. Besides its extremely low leakage power consumption, resistive memory (e.g., spin-transfer torque RAM) is also immune to the radiation induced soft errors due to its magnetic field based storage. In this article, we propose to LEverage reSistive memory to enhance the Soft-error robustness and reduce the power consumption (LESS) of registers in the General-Purpose computing on GPUs (GPGPUs). Since resistive memory experiences longer write latency compared to SRAM, we explore the unique characteristics of GPGPU applications to obtain the win-win gains: achieving the near-full soft-error protection for the register file, and meanwhile substantially reducing the energy consumption with negligible performance degradation. Our experimental results show that LESS is able to mitigate the registers soft-error vulnerability by 86% and achieve 61% energy savings with negligible (e.g., 1%) performance degradation.

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

In many digital signal processing (DSP) applications, static random access memory (SRAM) based embedded memory and flip-flop based shift registers consume a significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory or flip-flop based shift registers are inefficient in terms of area and power. We propose spintronic domain wall memory (DWM) based embedded memories for DSP building blocks such as survivor-path memories and last-in first-out (LIFO) in Viterbi decoder, first-in-first-out (FIFO) register files in FFT processor and bitonic sorter, and input register of distributed arithmetic (DA) based FIR filter that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65 nm technology show that the DWM based design achieves significant area and power savings over the conventional SRAM and spin-transfer-torque RAM (STTRAM) based design approach. For 8 k-point FFT processor and Viterbi decoder, the DWM-based design shows 60.6% (8.4%) and 66.4% ( $-$ 1.7%) area and 60.3% (44.3%) and 60.0% (37.8%) power savings over the conventional SRAM (STTRAM) based design, respectively. For DA-based FIR filter, it achieves 15.7% area and 15.5% power savings over shift register based design.

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and ignorable leakage power. However, it suffers from the bad write latency and poor write power consumption. Therefore, it is difficult to replace entire SRAM with STT-RAM in the L1 cache, but we can relax the retention time of STT-RAM cell to improve its write performance and replace some of the SRAM capacity to reduce leakage power. In this paper, we propose a locality-aware approach for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. Based on the principle of cache locality, data block is mapped to SRAM firstly to reduce write latency and write energy, and is moved to volatile STT-RAM to reduce leakage power consumption. After a time period when there is no access of a data block in the volatile STT-RAM, we then stop its refresh operations to further reduce power consumption. Experimental results show that in comparison with the SRAM only L1 cache configuration, our hybrid cache configuration and data migration methodology reduce energy consumption by about 15–20%, with only nearly to 5% of latency overhead. Also when comparing to the STT-RAM only L1 cache configuration, we reduce memory access latency nearly to 20% with close or even better energy consumption.

Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric field control of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultrafast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory merges features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs-based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM, resistive RAM, and spin transfer torque RAM. MeRAM can achieve ultrafast switching (<1 ns), low switching energy (∼1 fJ), and compact cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$6\;F^2$</tex-math></inline-formula> with a shared source region, as well as nonvolatility. For another application, we propose the VCMA-MEJ-based TCAM, which will be referred to as MeTCAM, consisting of 4T-2MEJs. Since MeTCAM fully exploits the low power and high density features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math>$44\;F^2 $</tex-math></inline-formula> ) compared to previous works.

Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems

Nonvolatile memory (NVM) has many benefits compared to the traditional static RAM, such as improved reliability and reduced power consumption, but it has long write latency and limited write endurance. Scratchpad memory (SPM) is software-managed small on-chip memory for improving system performance and predicability. We consider SPM based on spin-transfer torque RAM, a type of NVM with high performance and good endurance. We present algorithms for allocating data variables to SPM and distribute write activity evenly in the SPM address space, in order to achieve wear-leveling and prolong the lifetime of NVM. We present two optimization algorithms for minimizing system CPU utilization subject to NVM lifetime constraints: 1) an optimal algorithm based on ILP and 2) an efficient heuristic algorithm that can obtain close-to-optimal solutions.