LER: Least-Error-Rate Replacement Algorithm for Emerging STT-RAM Caches

Abstract

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation. This is done by comparing the contents of the incoming block with lines in a cache set. Compared with Least Recently Used (LRU) algorithm, LER reduces the error rate by 2× with about 1.4% and 3.6% performance and dynamic energy consumption overheads, respectively. Moreover, LER imposes no area overhead to system.