Magnetic Random Access Memory Research Articles

Perspectives on field-free spin–orbit torque devices for memory and computing applications

The emergence of embedded magnetic random-access memory (MRAM) and its integration in mainstream semiconductor manufacturing technology have created an unprecedented opportunity for engineering computing systems with improved performance, energy efficiency, lower cost, and unconventional computing capabilities. While the initial interest in the existing generation of MRAM—which is based on the spin-transfer torque (STT) effect in ferromagnetic tunnel junctions—was driven by its nonvolatile data retention and lower cost of integration compared to embedded Flash (eFlash), the focus of MRAM research and development efforts is increasingly shifting toward alternative write mechanisms (beyond STT) and new materials (beyond ferromagnets) in recent years. This has been driven by the need for better speed vs density and speed vs endurance trade-offs to make MRAM applicable to a wider range of memory markets, as well as to utilize the potential of MRAM in various unconventional computing architectures that utilize the physics of nanoscale magnets. In this Perspective, we offer an overview of spin–orbit torque (SOT) as one of these beyond-STT write mechanisms for the MRAM devices. We discuss, specifically, the progress in developing SOT-MRAM devices with perpendicular magnetization. Starting from basic symmetry considerations, we discuss the requirement for an in-plane bias magnetic field which has hindered progress in developing practical SOT-MRAM devices. We then discuss several approaches based on structural, magnetic, and chiral symmetry-breaking that have been explored to overcome this limitation and realize bias-field-free SOT-MRAM devices with perpendicular magnetization. We also review the corresponding material- and device-level challenges in each case. We then present a perspective of the potential of these devices for computing and security applications beyond their use in the conventional memory hierarchy.

Interfacial Engineering Strategies for Efficient Spin–Orbit Torque Devices with Pt Alloys

To make spin–orbit torque magnetic random-access memories (SOT-MRAMs) become competitive enough to replace the contemporary memory architecture, it is of great importance to utilize conductive SOT materials that possess large damping-like spin–orbit torque (DL-SOT) efficiencies and back-end-of-line (BEOL) compatibility. In this work, we report a BEOL-compatible CoFeB/MgO-based heterostructure with the Pt–Cr alloy as the spin current source (SCS) and inserted a Pt/Co/Pt composite layer to achieve texture decoupling and ferromagnetic coupling. A thermally robust perpendicular magnetic anisotropy (PMA) of the hybrid heterostructure can be retained after annealing at 400 °C for 1 h, while maintaining large DL-SOT efficiencies of the annealed Pt–Cr alloys (ξDL ∼ 0.34 for Pt0.70Cr0.30). Additionally, by optimizing the current distribution with a resistive Pt spacer layer, it is possible to simultaneously enhance the current-to-effective field conversion ratio (Hzeff/I) and retain the apparent ξDL (ξDL ∼ 0.37 for Pt0.79Cr0.21). Moreover, the critical switching current density can be reduced from JcPt ∼ 2.0 × 107 A·cm–2 for Pt to JcPt0.70Cr0.30 ∼ 4.9 × 106 A·cm–2 for Pt0.70Cr0.30 without tampering the thermal stability of the annealed heterostructure. These interfacial engineering strategies provide directions to integrate Pt-based SCSs with large ξDL into a BEOL-compatible platform for future SOT-MRAM devices with PMA.

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

Switching current reduction in magnetoresistive random access memories

We present an approach for minimizing the critical current for the magnetization switching in magnetic tunnel junctions by optimizing the spatial distribution of the current density. We show that such a minimization is possible because critical current is determined by the condition of making one of the magnetization eigenstates grow in time. The excitation of the eigenstates is enhanced when the spatial distributions of the eigenstates and current density overlap. Critical current can be viewed as a functional of the current density spatial distribution and it can be minimized by optimizing this distribution. Such an optimization results in a major reduction of the critical current and increase of the switching efficiency, viz. the ratio between the energy barrier and critical current. The minimized critical current increases approximately linearly with the magnetic tunnel junction size, which is much slower than critical current for the case of a uniform current density. The optimized efficiency can be approximately a constant with respect to the magnetic tunnel junction size, which is much higher than the efficiency for the uniform current density. Additional optimization can be achieved by spatially modulating the material parameters, e.g., the saturation magnetization. The presented approach and obtained scaling of the critical current and efficiency offers opportunities for the magnetic tunnel junction optimization.

Voltage-gated spin-orbit torque switching in IrMn-based perpendicular magnetic tunnel junctions

In this work, IrMn-based perpendicular magnetic tunnel junctions (MTJs) are investigated. By inserting a thin W layer at an antiferromagnet/ferromagnet (AFM/FM) interface, we enhance the annealing temperature to 355 °C and obtain a high tunnel magnetoresistance ratio of 127%. Subsequently, field-free spin–orbit torque (SOT) switching of perpendicular MTJ is realized thanks to the in-plane exchange bias generated at the AFM/FM interface. Moreover, by applying a gate voltage, a coercive field is effectively decreased due to the voltage-controlled magnetic anisotropy (VCMA) effect. Finally, through the interplay of the SOT and VCMA effects, the critical switching current density is dramatically reduced by 73% (to 2.4 MA/cm2) and the total writing power consumption is decreased by 84% when a gate voltage of 0.76 V is applied. These findings pave the way for the practical applications of the IrMn-based perpendicular MTJs in low-power magnetic random-access memory.

BIST-Supported Cryogenic Write Trimming With In-MRAM Computing Case Study

In the processor-memory separated von- Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in- self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications.

Impact of Voltage Polarity on Time-Dependent Dielectric Breakdown of 1-nm MgO-Based STT-MRAM With Self-Heating Correction

Time-dependent dielectric breakdown (TDDB) lifetime of ultrathin (1 nm) MgO in spin-transfer torque magnetoresistive random access memory (STT-MRAM) devices has recently been shown to be driven by factors other than voltage alone. This study focuses on the specific role of asymmetry in the current flow for different polarity pulsing modes of voltage stress on the TDDB lifetime of 1-nm MgO. Numerical analysis, based on a 3-D heat-diffusion equation and spintronic simulations, has been performed to characterize the temperature rise in the devices for precise correction of self-heating to obtain a correct interpretation of MgO TDDB. It is shown that the different lifetimes for the positive and negative modes can be attributed to different temperature increases arising from self-heating. While the positive and negative modes displayed a non-Arrhenius behavior, the bipolar mode showed an Arrhenius trend in which we observed a unique bimodal behavior of TDDB activation energy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {a}}$ </tex-math></inline-formula> ) as a function of stress voltage in the ultrathin MgO stack. We discuss the role of additional driving forces, such as current, self-heating, charge trapping, and interface strain governing the breakdown mechanism along with the voltage effect.

The magnetization reversal driven by spin-orbit-assisted spin-transfer torque

As the data writing scheme of magnetization reversal driven by spin-transfer torque can overcome the shortcomings of traditional magnetic-field writing mechanism, it has become a mainstream way of implementing information writing in magnetic random access memory. However, the explosive growth of information shows higher requirements for data storage and information processing, thus magnetic random access memories based on spin-transfer torque data writing method pose several issues, including barrier reliability and limited storage speed. Recent experimental studies have shown that the spin-orbit torque through the spin Hall effect or Rashba effect in heavy-metal/ferromagnetic bilayer structures has the potential advantages in overcoming these limitations. They can also be used to drive magnetization to achieve rapid reversal. Especially, the three-terminal magnetic tunnel junction separates data reading from writing current. It has the advantages of faster writing speed and better stability and thus becomes the most promising magnetic storage technique at present. The magnetization reversal driven by spin-orbit-assisted spin-transfer torque in a three-terminal magnetic tunnel junction is studied theoretically in this work. By linearizing the Landau-Lifshitz-Gilbert equation with the additional spin-transfer torque term and spin-orbit torque term in the spherical coordinates, two coupled differential equations and the new equilibrium directions are obtained. With the stability analysis of the new equilibrium directions, the phase diagrams defined in parameter space spanned by the current densities of spin-transfer and spin-orbit torques are established. There are several magnetic states in the phase diagrams, including quasi-parallel stable states, quasi-antiparallel stable states, and bistable states. By adjusting the current density of the spin-transfer torque, the magnetization reversal between two stable states is realized. It is found that the magnetization reversal time is greatly reduced with the assisting of spin-orbit torque, and it decreases with the augment of current density of spin-orbit torque. Meanwhile, the zero-field magnetization reversal can be realized through the interplay between spin-orbit torque and spin-transfer torque. In addition, compared with the damping-like term of spin-orbit torque, the field-like one plays a leading role in magnetization reversal. The presence of field-like term of spin-orbit torque can also reduce the reversal time that decreases with the increase of the ratio of field-like torque to damping-like one.

Giant tunneling magnetoresistance in in-plane double-barrier magnetic tunnel junctions based on MXene Cr2C.

The discovery of two-dimensional (2D) magnetic materials makes it possible to realize in-plane magnetic tunnel junctions. In this study, the transport characteristics of an in-plane double barrier magnetic tunnel junction (IDB-MTJ) based on Cr2C have been studied by density functional theory combined with the nonequilibrium Green's function method. The results showed its maximum tunneling magnetoresistance ratio (TMR) value reached 6.58 × 1010. Its minimum TMR value (3.86 × 106) was also comparable to those of conventional field effect transistors (FETs). Due to its giant TMR and unique structural characteristics, the IDB-MTJ based on Cr2C has great potential applications in magnetic random access memory (MRAM) and logic computing.

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel cell (MLC) STT-MRAM can further increase density by storing 2 bits in one cell’s hard and soft domain, respectively. However, MLC STT-MRAM suffers two-step write, leading to high write energy, long latency, and severe lifetime degradation. Current encoding techniques propose to encode the new data to reduce the two-step data writes. However, they have two weaknesses: 1) high area overhead, e.g., recent work TSE (Hsieh et al., 2020) needs extra 37.5% MLCs and 2) prolong the write latency due to an extra read. Therefore, we propose enhanced one-step write (EOSwrite) to write data in one step. EOSwrite includes line bypassing and four intraline encoding techniques. Line bypassing schemes can bypass the writes to zero or clean lines, leading to low write/read latency. As for the intraline techniques, we propose four write modes. They utilize the data patterns and the clean data in cache lines to write data in one step, therefore reducing the data write latency. The key idea of one-step write is to write as much data as possible in the soft domain of MLC STT-MRAM. EOSwrite can greatly relieve the weaknesses of the current encoding schemes. Evaluation results show that EOSwrite can improve the lifetime of MLC STT-MRAM by 56.96%, reduce dynamic energy by 33.95%, reduce access latency by 36.95%, and improve system performance of MLC STT-MRAM by 4.30%, respectively. While the area overhead of EOSwrite is only 7.27%.

Giant unilateral electric-field control of magnetic anisotropy in MgO/Rh2CoSb heterojunctions.

A large voltage-controlled magnetic anisotropy (VCMA) effect is highly desirable for applications of voltage-torque magnetic random access memory. In this work, the dependence of magnetic anisotropy (MA) on the electric field in a MgO-based heterojunction consisting of a new Heusler alloy, Rh2CoSb, is studied using first-principles calculations. We find that the Rh-terminated MgO/Rh2CoSb heterojunction has a perpendicular MA and a giant VCMA coefficient of 7024 fJ V-1 m-1. Furthermore, the VCMA coefficient shows a characteristic of dependence on the electric-field direction. The origins of these behaviors are elucidated by orbital-resolved MA and second-order perturbation theoretical analysis. As the spin-down states of the in-plane orbital, dxy, are close to the Fermi level, the shift of these states induced by the electric field gives rise to significant changes of magnetic anisotropy energy, which is mainly responsible for the giant VCMA effect.

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory

Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access Memory

In non-volatile random-access memory (RAM) technologies, the spin-torque transfer magnetic random-access memory (STT-MRAM) is a promising candidate. STT-MRAM has attracted attention owing to its advantages, such as a high density, high endurance, and high-speed writing/reading. Moreover, STT-MRAM is utilized to replace dynamic random-access memory (DRAM) in Internet of Things (IoT) and artificial intelligence (AI) applications. However, because the magnetic tunnel junction is used to write data, STT-MRAM must face process variation and thermal fluctuation problems. This causes errors in writing and reading processes. These errors are independent of each other. Therefore, to solve them and increase the reliability of STT-MRAM, the data are encoded before storage in STT-MRAM devices. In this study, we propose a method for designing codewords using modulation coding techniques. Our codewords increase the minimum Hamming distance and inheritance of the sparse code characteristic to exploit the asymmetric probability of the write errors. The simulation results show that our codewords can improve the bit error rate performance of STT-MRAM compared with previous works.

WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges

Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power. However, Spin Transfer Torque Magnetic RAM (STT-MRAM) suffers from three reliability issues, namely, read disturbance, write failure, and retention failure, that present significant challenges to its use as a reliable on-chip memory. All of these three reliability challenges become even more threatening with any increase in STT-MRAM cell temperature. Write operations are regarded as the main source of heat generation and temperature increase in STT-MRAM on-chip memories. This article first presents experiments to show how the heat generated by consecutive writes affects the reliability of an STT-MRAM on-chip cache. Then, it proposes the WiSE framework, an approach to reduce the STT-MRAM-based cache memory temperature and improve its reliability. WiSE utilizes the Reinforcement Learning (Reinforcement Learning (RL)) technique to detect high-density write operation patterns in STT-MRAM cache. To manage the write operations across the STT-MRAM caches, WiSE introduces a new temperature-aware replacement policy. The simulation results show that while WiSE imposes only about 1% performance overhead, it improves retention failure rate, read disturbance rate and write failure rate by 64%, 57%, and 47%, respectively, compared to Least Recently Used (Least Recently Used (LRU)) replacement policy.

Energy efficient ternary computation unit using differential spin Hall effect MRAM

Recent advances in quantized neural networks (QNNs) have paved the way for energy efficient hardware architectures for machine learning tasks. Binary and ternary QNNs are suitable for image classification and recognition applications on highly resource constrained hardware. Binary neural networks have low precision thus suffer a significant accuracy loss for dense networks and large datasets. This issue can be resolved through ternary neural networks (TNNs) with higher weight precision and better resource utilization. TNN implementation using conventional complementary metal oxide semiconductor and memristive devices show limited improvement in area and energy efficiency. Spintronics based magnetic random access memory (MRAM) devices are the most prominent choice amongst the various non-volatile memories for neural networks. This work presents the implementation of differential spin Hall effect (DSHE) MRAM-based two and three input ternary computation units (TCUs) for TNN. Furthermore, a multilayer perceptron architecture with synaptic crossbar array using the proposed TCU is implemented for Modified National Institute of Standards and Technology data classification. The results show that DSHE-based TCU is 30% more energy efficient as compared with spin-transfer torque (STT)-MRAM based design. Furthermore, DSHE-MRAM based TNN shows improvement in energy and area by 82% and 9%, respectively, when compared to STT-based TNN.

Sputter Gas Damage in Nanolayered Pt/Co/Ir-based Synthetic Antiferromagnets for Top-Pinned Magnetic Tunnel Junctions

We examine the role of sputter damage on limiting the perpendicular magnetic anisotropy and interlayer exchange coupling in Pt/Co/Ir-based synthetic antiferromagnets, a key building block used in the microelectronics community for standalone and embedded magnetic random access memories. By replacing the more conventional Ar process gas with Kr or Xe, we reduce the energy of backscattered sputter gas ions bombarding the substrate from in excess of 100 eV to a few 10 s of eV. Reducing this kinetic bombardment is critical to avoid intermixing of this nanolayered functional heterostructure, with the constituent Pt, Co, and Ir layer thicknesses each below 1 nm. Our approach leads to a simultaneous enhancement in the perpendicular magnetic anisotropy (>2 × 106 J/m3) and interlayer exchange coupling energy (>3.5 mJ/m2). This advantageous improvement in perpendicular anisotropy and interlayer exchange coupling is evident on a 5 nm-thick Pt buffer layer and additionally on an MgO/CoFeB/Mo underlayers complex, showing that this method can improve the performance of both top- and bottom-pinned reference layers in perpendicular magnetic tunnel junction devices. These experimental findings may help advance the processing of conventional and synthetic antiferromagnetic devices for emerging spintronic memory technologies.

Giant and strain-tunable interfacial magnetic anisotropy in MgO-based magnetic heterostructures with heavy atoms insertion

MgO-based magnetic heterostructures with interfacial magnetic anisotropy has attracted increasing attention due to its application in building high-density magnetic random access memories. A large and tunable interfacial magnetic anisotropy constant (Ki) is required for high thermal stability and flexible data writability. In this study, the Ki of Fe/MgO, Fe/Pt/MgO, and Fe/Ir/MgO heterostructures with strains from −4.5% to 4.5% were calculated by ab initio electronic structure calculations. It has been found that the Fe/Pt/MgO and Fe/Ir/MgO where the Pt and Ir monolayers are inserted in the interface possess Ki of 2.415 mJ m−2 and −4.468 mJ m−2, which are much larger by several times than that (0.840 mJ m−2) of the Fe/MgO. In particular, the out-of-plane Ki from the interfacial Pt atoms in Fe/Pt/MgO is as high as 5.978 mJ m−2. The magnetic anisotropy of these structures can be significantly manipulated by strain. Combining second-order perturbation theory, the origin of these behaviors has been analyzed by layer-resolved, orbital-resolved, and k-resolved Ki. The spin-flip terms of d z 2/d yz orbitals in the interfacial layer are mainly responsible for the out-of-plane Ki and its variation with strain. This work provides a useful guide for the design of high and tunable magnetic anisotropy in the MgO-based magnetic heterostructures.

Highly efficient spin current source using BiSb topological insulator/NiO bilayers

BiSb is a topological insulator with both giant spin Hall effect and high electrical conductivity, which are important for ultralow power spin–orbit-torque magnetoresistive random access memory. However, when a ferromagnetic (FM) thin film is deposited on top of BiSb, large surface roughness and diffusion of Sb out of the BiSb layer into the FM layer results in a much smaller effective spin Hall angle In this work, we show that by inserting a NiO layer between BiSb and Co, we can significantly improve of BiSb and induce perpendicular magnetic anisotropy at the NiO/Co interface. We obtained a large = 10.3 for the BiSb bottom layer at the NiO layer thickness of 3 nm, which is comparable to the best of BiSb top layer studied so far. Our study shows that BiSb/NiO bilayers are promising for integration of BiSb to SOT-MRAM.

High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM.

Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%.

Process-induced magnetic tunnel junction damage and its recovery for the development of spin–orbit torque magnetic random access memory

The generation of torques in heterostructures of heavy metals and ferromagnets (HM / FM) in spin–orbit torque magnetic random access memory (SOT-MRAM) makes them interesting for the development of magnetic memory technology. Currently, the emerging SOT-MRAM technology faces major challenges in etching based on current manufacturing tools. In that respect, we experimentally investigate the two different etching recipes (namely, CF-Etch, & NH-Etch) of the reactive ion etching (RIE) process on the performance of a Ta/CoFeB/MgO/Ta (hard mask) magnetic film stacks to develop the SOT-MRAM technology. The experimental results demonstrate that CF-Etch etches Ta very fast, and MgO etches very slowly. In contrast, NH-Etch etches those two materials at a comparable rate. Both etches are terminated before MgO is removed. Based on the experimental results, we found that the CF-Etch reduces the interfacial anisotropy of CoFeB/MgO films. Moreover, the CF-Etch also destroys the magnetic moment of CoFeB film, which further deteriorates after the annealing process. In contrast, the magnetic properties of the stack are only slightly affected when the NH-Etch recipe is used. We also discuss the advantages and disadvantages of these two recipes based on the experimental study. Finally, we developed the SOT-MRAM devices based on these two etching recipes of the RIE process to improve the etching yield of this technology. The current SOT-MRAM fabrication process enables a uniform etch stop on the thin tunnel barrier layer and the Ta heavy metal layer (HM). A wafer-level statistical study of SOT switching characteristics, including tunnel magnetoresistance (TMR), SOT switching thresholds, and parallel/antiparallel state resistances (RP/RAP), has been performed.