Spin Transfer Torque Magnetic Random Access Memory Research Articles

A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Green's function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient design paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting design requirements for read stability, writability and cell area. It can be used at an early stage of the design cycle for yield enhancement.

Design Consideration of Magnetic Tunnel Junctions for Reliable High-Temperature Operation of STT-MRAM

Commercializing spin-transfer-torque magnetic random access memory (STT-MRAM) requires thorough investigation of magnetic tunnel junctions (MTJs) at temperature corners. In this paper, high-temperature behaviors of MTJs are investigated in conjunction with temperature-dependent transistor characteristics in order to ensure reliable high-temperature operation of STT-MRAM.

Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.

차세대 자기저항메모리 MRAM 기술의 특허동향 분석

차세대 메모리 소자 중 MRAM(Magnetic Random Access Memory)은 자기저항효과를 이용한 비휘발성 메모리로 기존 메모리를 대체할 것으로 주목을 받고 있다. MRAM은 자기터널 접합 소자를 이용해 구동할 수 있는데, 현재 고집적, 저 전력 소모 등의 장점을 극대화하기 위해 수직자화 특성을 갖는 자기터널 접합 개발과 스핀전달토크를 이용해 구동하는 STT-MRAM(Spin Transfer Torque-MRAM) 개발이 활발히 이루어지고 있다. 따라서 미국, 일본 등 MRAM 강국에서 고집적, 스위칭 전류 감소, 열적 안정성 등의 문제를 해결하기 위한 기술 특허 출원이 증가하고 있으며, 국내의 MRAM 연구기관에서의 특허 출원도 꾸준히 이루어지고 있다. 본고에서는 기존 국내외 특허 출원 및 등록 경향을 분석하고 향후 MRAM 개발방향을 제시하였다. Among the next generation memory, MRAM (Magnetic Random Access Memory) is worthy of notice for substituting the preexisting memory thanks to its non-volatile property and other advantages. Recently perpendicular MRAM and spin transfer torque MRAM techniques are under active investigation to realize a high density and low power consumption. As a result, there are increasing of patents applications for high density, low current density for magnetization switching and high thermal stability. In this paper, we analyze the trend of patent applications and registrations about MRAM and propose a direction of future investigation.