Spin Transfer Torque Magnetic Random Access Memory Research Articles

Performance Analysis of Spin Orbit Torque Magneto-Resistive RAM Caches in 4-core ARM Systems

Spin Orbit Torque Magnetic Random Access Memory (SOT–)MRAM is gaining interest as it eradicates several limitations posed by its predecessor Spin Transfer Torque (STT-)MRAM, yet inherits all its advantages. This work explores in detail, the suitability of SOT–MRAM implemented caches in different levels of memory hierarchy in comparison to conventional SRAM technology, over several performance parameters like area, energy consumption and execution time for an embedded benchmark suite. Our circuit-level analysis shows that SOT–MRAM outperforms SRAM for caches ([Formula: see text] KB), and only lags in area and read-access energy for smaller caches. A typical 512 KB SOT–MRAM cache improves area by 1%, read/write latency by 33/38%, and leakage by over 99% than that of SRAM memory technology. The architecture-level analysis confirms that on average SOT–MRAM is energy efficient by 74% in L1, 97.2% in L2 and 89.3% in both (i.e., L1 + L2) implementations against SRAM, for a 22[Formula: see text]nm technology node. We also estimate that SOT–MRAM only solution offers [Formula: see text]% energy savings and [Formula: see text]% better EDP than Hybrid (L1-SRAM and L2-SOT) memory hierarchy for multi-core ARM processors.

The single event upset hardened design of spin transfer torque magnetic random access memory read circuits at 40 nm technology

With the advancement of technology nodes, the challenging space radiation environment poses a significant threat to memory reliability. Spin transfer torque magnetic random access memory (STT-MRAM) is a formidable candidate for non-volatile memory for space applications due to its advantages of non-volatility, durability, speed and compatibility with CMOS technology. Although the STT-MRAM memory unit magnetic tunnel junction (MTJ) is naturally immune to radiation effects, the single event upset (SEU) affects the peripheral circuitry. A radiation-hardened circuit is proposed, which theoretically does not have ‘0' upset nodes and automatically recovers from ‘1' upset. Moreover, the circuit's radiation-hardened performance was corroborated through hybrid simulation utilizing 40-nm technology. The findings of this investigation hold significance for the use of space radiation-hardened STT-MRAM.

Magnetic tunnel junctions with superlattice barriers

The urgent demand for high-performance emerging memory, propelled by artificial intelligence in internet of things (AIoT) and machine learning advancements, spotlights spin-transfer torque magnetic random-access memory as a prime candidate for practical application. However, magnetic tunnel junctions (MTJs) with a single-crystalline MgO barrier, which are central to magnetic random-access memory (MRAM), suffer from significant drawbacks: insufficient endurance due to breakdown and high writing power requirements. A superlattice barrier-based MTJ (SL-MTJ) is proposed to overcome the limitation. We first fabricated the MTJ using an SL barrier while examining the magnetoresistance and resistance-area product. Lower writing power can be achieved in SL-MTJs compared to MgO-MTJs. Our study may provide a new route to the development of MRAM technologies.

Complementary Polarizer SOT-MRAM for Low-Power and Robust On-Chip Memory Applications

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area.

Mixed etching-oxidation process to enhance the performance of spin-transfer torque MRAM for high-performance computing

Spin-transfer torque magnetic random access memory (MRAM) devices have considerable potential for high-performance computing applications; however, progress in this field has been hindered by difficulties in etching the magnetic tunnel junction (MTJ). One notable issue is electrical shorting caused by the accumulation of etching by-products on MTJ surfaces. Attempts to resolve these issues led to the development of step-MTJs, in which etching does not proceed beyond the MgO barrier; however, the resulting devices suffer from poor scalability and unpredictable shunting paths due to asymmetric electrode structures. This paper outlines the fabrication of pillar-shaped MTJs via a four-step etching process involving reactive-ion etching, ion-beam etching, oxygen exposure, and ion-trimming. The respective steps can be cross-tuned to optimize the shape of the pillars, prevent sidewall redeposition, and remove undesired shunting paths in order to enhance MTJ performance. In experiments, the proposed pillar-MTJs outperformed step-MTJs in key metrics, including tunneling magnetoresistance, coercivity, and switching efficiency. The proposed pillar-MTJs also enable the fabrication of MRAM cells with smaller cell sizes than spin–orbit torque devices and require no external field differing from voltage-controlled magnetic anisotropy devices.

Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems

Convolutional Neural Networks (CNNs) have significantly impacted embedded system applications across various domains. However, this exacerbates the real-time processing and hardware resource-constrained challenges of embedded systems. To tackle these issues, we propose spin-transfer torque magnetic random-access memory (STT-MRAM)-based near memory computing (NMC) design for embedded systems. We optimize this design from three aspects: Fast-pipelined STT-MRAM readout scheme provides higher memory bandwidth for NMC design, enhancing real-time processing capability with a non-trivial area overhead. Direct index compression format in conjunction with digital sparse matrix-vector multiplication (SpMV) accelerator supports various matrices of practical applications that alleviate computing resource requirements. Custom NMC instructions and stream converter for NMC systems dynamically adjust available hardware resources for better utilization. Experimental results demonstrate that the memory bandwidth of STT-MRAM achieves 26.7 GB/s. Energy consumption and latency improvement of digital SpMV accelerator are up to 64× and 1,120× across sparsity matrices spanning from 10% to 99.8%. Single-precision and double-precision elements transmission increased up to 8× and 9.6×, respectively. Furthermore, our design achieves a throughput of up to 15.9× over state-of-the-art designs.

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

Binary neural networks (BNNs) are the most efficient solution to bridge the design gap of the hardware implementation of neural networks in a resource-constrained environment. Spintronics is a prominent technology among emerging fields for next-generation on-chip non-volatile memory. Spin transfer torque (STT) and spin-orbit torque (SOT) based magnetic random-access memory (MRAM) offer non-volatility and negligible static power. Over the last few years, STT and SOT-based multilevel spintronic memories have emerged as a promising solution to attain high storage density. This paper presents the operation principle and performance evaluation of spintronics-based single-bit STT and SOT MRAM, dual-level cells, three-level cells (TLCs), and four-level cells. Further, multi-layer perceptron architectures have been utilized to perform MNIST image classification with these multilevel devices. The performance of the complete system level consisting of crossbar arrays with various MRAM bit cells in terms of area, energy, and latency is evaluated. The throughput efficiency of the BNN accelerator using TLCs is 26.6X, and 3.61X higher than conventional single-bit STT-MRAM, and SOT-MRAM respectively.

A Radiation-Hardened Triple Modular Redundancy Design Based on Spin-Transfer Torque Magnetic Tunnel Junction Devices

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation.

Data-cell-variation-tolerant triple sampling non-destructive self-reference sensing scheme of STT-MRAM

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption.

Advanced hybrid MRAM based novel GPU cache system for graphic processing with high efficiency

With the rapid development of portable computing devices and users’ demand for high-quality graphics rendering, embedded Graphics Processing Units (GPU) systems for graphics processing are increasingly turning into a key component of computer architecture to enhance computability. The cache system based on traditional static random access memory (SRAM) plays a crucial role in GPUs. But high leakage, low lifetime and poor integration problems deeply plague the science and engineering field. In the paper, a novel magnetic random access memory (MRAM) based cache architecture of GPU systems is proposed for highly efficient graphics processing and computing accelerating, with the merits of high speed, long endurance, strong interference resistance, and ultra-low power consumption. Spin transfer torque-MRAM and spin orbit torque-MRAM are utilized in off-chip and on-chip caches, respectively. A controller design scheme with prefetching modules and optimized cache coherency protocols are adopted. After testing and evaluating with multiple loads, neural network models and datasets, the simulation results show that the proposed system can achieve up to 28%, 56%, and 66.45% optimizations mostly in terms of speed, energy and leakage power, respectively.

A novel time-domain in-memory computing unit using STT-MRAM

Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.

Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Due to high static power and low scalability, the traditional SRAM-based cache is not a good solution for image processing applications. Emerging Spin Transfer Torque Magnetic RAM (STT-MRAM) is a promising candidate for cache due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. Therefore, by making use of the ability of tolerating minor errors in image processing applications, this work presents an STT-MRAM based APProximate cache architecture (APPcache+) to write/read approximate data, which can largely reduce the cache energy and improve the STT-MRAM lifetime. APPcache+ includes three main designs. Firstly, we find that there are many similar elements (e.g., pixels in images) in cache lines. Therefore, APPcache+ presents several lightweight similarity-based encoding techniques to remove redundant elements, thus shortening the data size and reducing the energy of STT-MRAM cache. Secondly, we design a partial read scheme to reduce the read energy of the STT-MRAM cache. In the traditional decompression process, the whole line is fetched into the decompressor, leading to unnecessary read energy. The partial read scheme can largely reduce read energy while keeping the overhead low. Thirdly, we observe the encoding schemes may lead to bit write imbalance. Therefore, we propose a lightweight Ping-Pong intra-line wear-leveling scheme to improve the lifetime. Compared with the baseline, extensive evaluation results show that our APPcache+ can largely reduce the overall energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation and 1.86% output quality loss.

Deep-Learning-Based Adaptive Error-Correction Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising emerging non-volatile memory (NVM) technology with wide applications. However, the data recovery of STT-MRAM is affected by the diversity of channel raw bit error rate (BER) across different dies caused by process variations, as well as the unknown resistance offset due to temperature change. Therefore, it is critical to develop effective decoding algorithms of error correction codes for STT-MRAM. In this paper, we first propose a neural bit-flipping (BF) decoding algorithm, which can share the same trellis representation as the state-of-the-art neural decoding algorithms, such as the neural belief propagation (NBP) and neural offset min-sum (NOMS) algorithm. Hence a neural network (NN) decoder with a uniform architecture but different NN parameters can realize all these neural decoding algorithms. Based on such a unified NN decoder architecture, we further propose a novel deep learning (DL)-based adaptive decoding algorithm whose decoding complexity can be adjusted according to the change of the channel conditions of STT-MRAM. Extensive experimental evaluation results demonstrate that the proposed neural decoders can greatly improve the performance over the standard decoders, with similar decoding latency and energy consumption. Moreover, the DL-based adaptive decoder can work well over different channel conditions of STT-MRAM irrespective of the unknown resistance offset, with a 50% reduction of the decoding latency and energy consumption compared to the fixed decoder.

Power-Aware Quantization in Analog In-Memory Computing With STT-MRAM Macro

Analog in-memory computing (AiMC) reduces the cost of data transfer by processing data inside memory. Compared with other emerging nonvolatile memories, AiMC with magnetic random-access memory (MRAM) shows potential with logic compatible supply voltage, small variability issues, and high endurance. However, the analog output of the array must be converted to digital using an analog-to-digital converter (ADC), which significantly offsets the benefits of AiMC. This paper presents power-aware quantization circuits in AiMC with spin transfer torque MRAM (STT-MRAM) macro, in which a successive approximation register (SAR) ADC with reconfigurable 3/4-bit resolution and 250MS/s sampling rate addresses the need of high speed and low power for AiMC. By using 28-nm CMOS process, simulation results show that the proposed ADC consumes only 31.6 μW at a 900mV supply and 250MS/s. 10.4-25.7 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN).

Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.

MTJ-based random number generation and its application in SNN handwritten digits recognition

Spiking Neural Networks (SNNs) that require synapse weight initialization using random numbers have been widely used in the neural morphological system. However, the random numbers generated by traditional digital circuits have certain repeatability, and the entire computing architecture has issues such as high resource consumption and low integration. In this letter, a hardware system for true random number generation is realized through integrating a magnetic tunnel junction, a memory cell of MRAM (magnetic random access memory) chips, with an interface circuit and using the same mechanism as writing data in spin transfer torque MRAM. The generated true random numbers are evaluated using NIST SP800-22 standard and are used for synapse weight initialization in an SNN system. The recognition rate of the system initialized by the generated true random numbers is about 84% for an MNIST handwritten digit dataset, which is 2%–3% higher than that using a traditional linear feedback shift register. The reported work provides a new approach for better SNN performance.

Experimental and Theoretical Investigation of Intracell Magnetic Coupling-Induced Variability of Spin-Transfer Torque Magnetic RAMs

Experimental and Theoretical Investigation of Intracell Magnetic Coupling-Induced Variability of Spin-Transfer Torque Magnetic RAMs

A high-speed and power-efficient gradient-pulse injection method for spin-transfer torque magnetic random-access memory

With the development of modern computer storage technology, the spin-transfer torque magnetic random-access memory (STT-MRAM) has become one of the most promising candidates to replace the static random-access memory and dynamic random-access memory. However, its large power consumption and long relaxation time before the magnetic moments switch are important factors restricting its commercial application. In this work, gradient-current pulses are proposed to replace the conventional constant-current pulses in the injection method. A 70-nm classical CoFeB/MgO/CoFeB magnetic tunnel junction (MTJ) with perpendicular magnetic anisotropy was simulated and measured at pulse widths of 20, 30, and 40 ns using the proposed and conventional injection pulses. The comparison results show that adopting gradient pulses can significantly reduce the relaxation time and switching power consumption of the MTJ. A power consumption reduction of 8%–40% is obtained at different pulse amplitudes and widths. Our method paves an avenue for overcoming the issues affecting the STT-MRAM and could help to promote its commercial applications.

Computing in-memory with cascaded spintronic devices for AI edge

Spin-transfer-torque magnetic random access memory (STT-MRAM) shows great advantages for computing in-memory (CIM), which has emerged as a popular research direction to overcome the “memory wall” bottleneck in artificial intelligence (AI) applications. In this work, a magnetoresistance accumulation based computing in STT-MRAM (MA-CIM) framework using cascaded magnetic tunnel junctions is proposed for binary neural networks (BNN) inference. A SAR-like sensing scheme is elaborated to generate parallel multi-channel convolution results. Simulation analysis and layout design were performed using an industrial 28-nm CMOS process. MNIST and CIFAR-10 image recognition were executed with MA-CIM and the inference accuracy can reach 97.2% and 81.3%, respectively. Compared to current accumulation, the energy efficiency improves by 1.24× to 92.3 TOPS/W. The proposed MA-CIM framework improves the parallelism and energy efficiency of in-MRAM-computing, making it suitable for a wide range of AI applications requiring high energy efficiency at the edge, such as image recognition and speech recognition.