Spin Transfer Torque Magnetic Random Access Memory Research Articles

Variation-Tolerant High-Reliability Sensing Scheme for Deep Submicrometer STT-MRAM

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM's wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance.

Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors

Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.

Variation-Tolerant and Disturbance-Free Sensing Circuit for Deep Nanometer STT-MRAM

This paper presents a high reliability sensing circuit for the deep nanometer spin-transfer torque magnetic random-access memory (STT-MRAM). This sensing circuit, using a triple-stage sensing operation and source follower charge transfer amplification, is able to tolerate mostly the process, voltage, and temperature variations, thus improving greatly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance. With the STMicroelectronics CMOS 40-nm design kit and a precise STT-MTJ compact model, Monte-Carlo simulations have been performed to evaluate its sensing reliability performance.

Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Spin transfer torque (STT) magnetic random access memories (MRAMs) have recently emerged as one of the strongest contenders for universal memory technology. They have entire range of features, i.e., high speed, nonvolatility, high density, and low power, which make them cynosure to every memory designer's notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a larger amount of embedded memory, the cell size must be reduced. Therefore, the designs target to attain an optimistic figure of 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (F being the feature size) array density, which is the maximum achievable two-dimensional (2-D) density. With this objective in mind, a novel 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source NMOS transistor is proposed. The magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical GAA device structure. Furthermore, these TCAD results are used to calibrate the BSIM CG model for cylindrical GAA transistors. The proposed STT MRAM cell is then analyzed using calibrated Verilog-A models for perpendicular anisotropy MTJ and vertical GAA NMOS transistor (BSIM CG). The performance analysis in terms of read stability, write margins, and power dissipation for the proposed cell is also presented.

Depth-Dependent Magnetization Profiles of Hybrid Exchange Springs

Magnetic anisotropy is a central concept in spintronics, and while in-plane and perpendicular anisotropies dominate discussion, an arbitrarily tilted anisotropy would allow greater flexibility in designing magnetic storage and logic technologies. The authors directly measure the magnetization tilt angle in a so-called ``exchange spring'', and tune the angle by exploiting the system's competing anisotropies. This level of understanding is a significant step in developing e.g. spin transfer torque MRAM and spin torque oscillators.

Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective

In this paper, we propose a new spin-transfer torque magnetic random access memory (STT-MRAM) bit-cell structure (with complementary polarizers) that is suitable for on-chip caches. Our proposed structure requires a lower average critical write current than standard STT-MRAM, with improved write-ability, readability, and reliability. A cache array based on our proposed structure is studied using a device/circuit simulation framework, which we developed for this paper. Simulation results show that at the bit-cell level, our proposed structure can achieve subnanosecond sensing delay and lower read disturb torque using a self-referenced differential READ operation. Sensing and disturb margins of our proposed cell are 1.8× and 2.4× better than standard STT-MRAM, respectively. Furthermore, near disturb-free READ operation at ≥1.5 GHz is achieved using a latch-based sense amplifier and verified in circuit simulations. In addition, content addressable memory may also be efficiently implemented using complementary polarizer spin-transfer torque (CPSTT). Transient SPICE simulations show that CPSTT may be suitable for L1 cache, with a read energy of 14 fJ/bit. System level simulation shows that a CPSTT-based L2 cache can achieve ~9% lower energy consumption and >9% improvement in instructions per cycle over a standard STT-MRAM-based cache.

Domain-Specific Many-core Computing using Spin-based Memory

Spin-based devices have shown great potential in enabling high-density, energy-efficient memory and are therefore, considered highly promising for the design of future computing platforms. While the impact of spin-based devices on general-purpose computing platforms has been studied, they are yet to be explored in the context of domain-specific computing, where the characteristics of the devices can be matched to application characteristics through architectural customization, so as to maximize the benefits. We present the design and evaluation of a many-core domain-specific processor for the emerging application domains of Recognition and Mining (RM) using spin-based memories. The domain-specific processor has a two-level on-chip memory hierarchy consisting of a streaming access first-level memory and a random access second-level memory. Based on the memory access characteristics, we suggest the use of Domain Wall Memory (DWM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) to realize the first and second levels, respectively. We develop architectural models of DWM and STT-MRAM, and use them to evaluate the proposed design and explore various architectural tradeoffs in the domain-specific processor. We evaluate the proposed design by comparing it to a CMOS-based baseline at the same technology node. For three representative RM algorithms (support vector machine, k-means clustering, and generalized learning vector quantization), the spin-memory-based design achieves an energy-delay product improvement of 1.5 ×-4 × over the CMOS baseline at iso-area. Our results suggest that spin-based memory technologies can enable significant improvements in energy efficiency and performance for highly parallel, data-intensive workloads. Our study also highlights the importance of synergistic architectural exploration along with the use of emerging devices rather than simply considering them as drop-in replacements.

A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems

The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but still face the challenges of high saving power and area overhead, and low data reliability. This paper presents a new resistive Non-Volatile Memory (NVM) based circuit architecture with zero leakage power dissipation. It stores the states of the registers in the localized spin-torque-transfer magnetic random access memory (STT-MRAM) array through scan chains, which has reduced by more than 20% sleep energy than conventional nvFF schemes, and saved by more than 99.8% sleep energy compared to the retention CMOS register based approaches when the sleep time is longer than 1 s. Moreover, the proposed pipelined quad-phase saving scheme maximizes the saving speed, while reduces the peak saving current.

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

Modeling of In-Plane Magnetic Tunnel Junction for Mixed Mode Simulations

The incredible potentials of spin transfer torque (STT) magnetic random access memories (MRAMs) give them an edge over other memory technologies. Most of the projections show them as universal memory in the future; however, their evolution is still in a rudimentary stage. Attaining a high density in STT MRAMs is imperative to keep pace with the scaling scenario in field effect transistors (FETs) and hence competitive with future processors. A vertical or a two terminal select device can be a possible solution to achieve the high-density problem. A suitable platform is required for simulating a hybrid magnetic tunnel junction (MTJ)/FET circuit before an actual fabrication is done. However, most simulation tools do not have the capability to model hybrid MTJ/FET devices. Also, the SPICE compatible models for such devices and other novel structures like vertical FET are not available. This paper addresses the above-mentioned concerns and proposes a model for MTJ (coded in C++) and a simulation platform for hybrid MTJ/FET device-circuit co-design with physics-based models. The proposed model is validated using mixed mode simulations.

Different dielectric breakdown mechanisms for RF-MgO and naturally oxidized MgO

We investigate the voltage breakdown of the spin transfer torque magnetic random access memory (STT-MRAM) with perpendicular magnetic tunnel junctions (pMTJs). Different breakdown behaviors are observed for RF-MgO pMTJs and naturally oxidized MgO pMTJs. While the time-to-failure body distribution of the naturally oxidized MgO follows the Weibull distribution, that of RF-MgO follows the lognormal distribution. This result suggests distinctly different dielectric breakdown mechanisms for naturally oxidized MgO and RF-MgO. For low failure probability, the progressive voltage breakdown of RF-MgO (associated with the lognormal distribution) results in an order-of-magnitude reliability improvement over the abrupt breakdown of the naturally oxidized MgO. We show that RF-MgO is suitable for perpendicular STT-MRAM applications.

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies

Conventional spin transfer torque MRAM sensing circuits suffer from a small sensing margin and a large sensing margin variation in deep submicron technologies. The small sensing margin issue becomes worse in the low-leakage process technology due to the higher threshold voltage. In this brief, the self-body biasing (self-BB) scheme is proposed to resolve the small sensing margin issue. In the self-BB scheme, the threshold voltage of load pMOS is adaptively controlled by body bias. Although leakage current 'lows through the body due to the positive junction bias voltage, it is well suppressed to less than 1% (0.3 μA) of the sensing current and 'lows only during the sensing operation. To reduce large sensing margin variation, the source degeneration scheme with the longer channel length is used for the load pMOS. The HSPICE simulation results obtained using low-leakage 45-nm model parameters show that the proposed sensing circuit achieves a probability of the read access pass yield (PRAPY Memory) of 100%, whereas the sensing circuit without BB scheme has an PRAPY Memory of 5.8% for a 32-Mb memory with a sensing time of 2 ns.

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep sub-micron MOS technologies. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Transfer Torque MRAM (STT-MRAM) is considered the most promising NVM to address this issue thanks to its high speed, low power, and infinite endurance. However, one of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). In this paper, we propose a power-efficient MFF design architecture to address this challenge based on the combination of checkpointing operation, power gating and self-enable mechanisms. Multi non-volatile storages can be integrated locally in a conventional FF without significant area overhead benefiting from the 3-D implementation of STT-MRAM. We performed electrical simulations (i.e. transient and statistical) to validate its functional behaviors and evaluate its performance by using an accurate spice model of STT-MRAM and an industrial 40 nm CMOS design kit. The simulation results confirm its lower power consumption compared to conventional CMOS FF and the other structures.

Joule Heating and Peltier Effects in Thermoelectric Spin-Transfer Torque Mram Devices Using Finite Element Modeling

This paper reports the Joule heating and Peltier effects in thermoelectric spin-transfer torque MRAMs (TSTT-MRAMs). The simulation was undertaken based on the current-induced magnetization switching at the MgO/CoFe magnetic tunnel junction. Thermal and heat flux distributions of the TSTT-MRAM cells were simulated and analyzed using finite-element modeling. The Joule heating and Peltier effects lead to the increases in the temperature and heat flux distributions at the magnetic tunnel junction (MTJ) as well as the thermoelectric module. The maximum temperature of Peltier effect is higher than Joule heating effect when voltage amplitude below 0.77V. Some practical data for the STT-MRAM were also reported.

A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered one of the most promising non-volatile memory candidates thanks to its excellent performance in terms of access speed, endurance, and compatibility to CMOS. However, high power supply voltage is required in the conventional STT-MRAM writing circuit, which results in high power consumption (e.g., ~10 pJ/bit). In addition, it suffers from stochastic switching behavior and process voltage temperature variations. These make power-efficient and reliable write/read circuits become critical challenges. In this paper, we present novel circuits and architectures to build a 16 kb STT-MRAM design with low power and high reliability. For example, the self-enable switching scheme reduces the power consumption effectively and the fore-placed sense amplifier improves the robustness to process variation. Using an accurate compact model of 65 nm STT-MRAM and a commercial CMOS design kit, mixed transient and statistical simulations have been performed to validate this design.

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture-asymmetric write architecture with redundant blocks (AWARE)-that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions ( 1→ 0 and 0→ 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity.

Normally-off type nonvolatile static random access memory with perpendicular spin torque transfer-magnetic random access memory cells and smallest number of transistors

In this paper, we present a novel nonvolatile-random access memory (RAM) cell design based on a “normally-off memory architecture” using a perpendicular spin torque transfer-magnetic random access memory (STT-MRAM) based on a four-transistors static random access memory (SRAM) in order to reduce the operating power of mobile processors. After the cell design concept and basic operation are proposed, a stable and reliable operation for read/write is confirmed by circuit simulation.

Influence of hydrogen patterning gas on electric and magnetic properties of perpendicular magnetic tunnel junctions

To identify the degradation mechanism in magnetic tunnel junctions (MTJs) using hydrogen, the properties of the MTJs were measured by applying an additional hydrogen etch process and a hydrogen plasma process to the patterned MTJs. In these studies, an additional 50 s hydrogen etch process caused the magnetoresistance (MR) to decrease from 103% to 14.7% and the resistance (R) to increase from 6.5 kΩ to 39 kΩ. Moreover, an additional 500 s hydrogen plasma process decreased the MR from 103% to 74% and increased R from 6.5 kΩ to 13.9 kΩ. These results show that MTJs can be damaged by the hydrogen plasma process as well as by the hydrogen etch process, as the atomic bonds in MgO may break and react with the exposed hydrogen gas. Compounds such as MgO hydrate very easily. We also calculated the damaged layer width (DLW) of the patterned MTJs after the hydrogen etching and plasma processes, to evaluate the downscaling limitations of spin-transfer-torque magnetic random-access memory (STT-MRAM) devices. With these calculations, the maximum DLWs at each side of the MTJ, generated by the etching and plasma processes, were 23.8 nm and 12.8 nm, respectively. This result validates that the hydrogen-based MTJ patterning processes cannot be used exclusively in STT-MRAMs beyond 20 nm.

(Keynote) Requirements for the Emerging Memory Era

As current computing system is changing to cope with the exponential growth of data, memory device in the near future should be able to provide huge memory capacity with lower power consumption; changes stem not only from computing system architecture, but from memory hierarchy. However, conventional charge-based memories such as DRAM and FG NAND Flash memory have difficulties in scaling due to the limited number of charges. Therefore, lots of researchers are currently working on emerging memory devices for the future computing system. In this paper we introduce emerging memory devices such as Phase Change RAM (PCRAM), Spin-Transfer Torque MRAM (STT-MRAM), and Resistance change RAM (ReRAM). We discuss the characteristics and scalability of each memory device and summarize the requirements to open the era of emerging memory.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.