Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Abstract

Spin transfer torque (STT) magnetic random access memories (MRAMs) have recently emerged as one of the strongest contenders for universal memory technology. They have entire range of features, i.e., high speed, nonvolatility, high density, and low power, which make them cynosure to every memory designer's notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a larger amount of embedded memory, the cell size must be reduced. Therefore, the designs target to attain an optimistic figure of 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (F being the feature size) array density, which is the maximum achievable two-dimensional (2-D) density. With this objective in mind, a novel 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source NMOS transistor is proposed. The magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical GAA device structure. Furthermore, these TCAD results are used to calibrate the BSIM CG model for cylindrical GAA transistors. The proposed STT MRAM cell is then analyzed using calibrated Verilog-A models for perpendicular anisotropy MTJ and vertical GAA NMOS transistor (BSIM CG). The performance analysis in terms of read stability, write margins, and power dissipation for the proposed cell is also presented.