Low power STT MRAM cell with asymmetric drive current vertical GAA select device

Abstract

STT MRAMs are non-volatile memories potentially demonstrating high speed and integration density. These exclusive features of STT MRAMs are rapidly gaining attention of memory designers. They are strong contenders for futuristic embedded memory applications. Researchers have been primarily focusing on further decreasing the switching energy and increasing the integration density, while retaining the much important stability (i.e. non-volatility over large periods). Proceeding with a similar intent, this paper explores the next generation STT MRAM driven by asymmetric vertical silicon nano-wire gate all around (GAA) select device. The perpendicular magnetic anisotropy magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device. The inherent asymmetry in critical switching current of an MTJ is exploited by a matching asymmetric drive current select device that achieves a significant reduction in power dissipation. The analysis is carried out using SPICE simulations with calibrated Verilog-A models of vertical GAA device and perpendicular magnetic anisotropy MTJ. Encouragingly, the proposed design lowers the power dissipation up to 30% with a minimum cell area of 4F2 (F is the feature size).