Spin Orbit Torque Magnetic Random Access Memory Research Articles

Complementary Polarizer SOT-MRAM for Low-Power and Robust On-Chip Memory Applications

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area.

Large Field-like Spin-Orbit Torque and Enhanced Magnetization Switching Efficiency Utilizing Amorphous Mo.

Spin-orbit torque magnetic random access memory (SOT-MRAM) has great promise in high write speed and low power consumption. Mo can play a vital role in constructing a CoFeB/MgO-based MRAM cell because of its ability to enhance the perpendicular magnetic anisotropy (PMA), thermal tolerance, and tunneling magnetoresistance. However, Mo is often considered as a less favorable candidate among SOT materials because of its weak spin-orbit coupling. In this study, we experimentally investigate the SOT efficiencies in Mo/CoFeB/MgO heterostructures over a wide range of Mo thicknesses and temperature. Decent damping-like SOT efficiency |ξDL| = 0.015 ± 0.001 and field-like SOT efficiency |ξFL| = 0.050 ± 0.001 are found in amorphous Mo. The ξFL/ξDL ratio is greater than 3. Furthermore, efficient current-induced magnetization switching is demonstrated with the critical current density comparable with heavy metal Ir and W. Our work reveals new understanding and possibilities for Mo as both an SOT source component and PMA buffer layer in the implementation of SOT-MRAMs.

Field-Free Spin-Orbit Torque Magnetization Switching in a Perpendicularly Magnetized Semiconductor (Ga,Mn)As Single Layer.

Current-induced spin-orbit torque (SOT) in a perpendicularly magnetized single layer has a strong potential to switch the magnetization using an extremely low current density, which is generally 2-3 orders of magnitude smaller than that required for conventional metal bilayer systems. However, an in-plane external magnetic field has to be applied to break the symmetry and achieve deterministic switching. To further enhance the high-density integration and accelerate the practical application of highly efficient SOT magnetic random-access memory (SOT-MRAM) devices, field-free SOT magnetization switching in a ferromagnetic single layer is strongly needed. In a spin-orbit ferromagnet (a ferromagnet with strong spin-orbit interaction) with crystal inversion asymmetry and a multi-domain structure, the internal Dzyaloshinskii-Moriya effective fields are considered to induce field-free switching. Here, combined with strong spin-orbit coupling and a tilted anisotropy axis induced by a nonuniform Mn distribution and a possible magnetocrystalline anisotropy resulting from a slight substrate tilting, we successfully achieve magnetization switching in a spin-orbit ferromagnet (Ga,Mn)As single layer by utilizing SOT without applying any external magnetic field. Our findings help to deeply elucidate the SOT switching mechanism and can advance the development of a highly efficient MRAM with better scalability.

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

Binary neural networks (BNNs) are the most efficient solution to bridge the design gap of the hardware implementation of neural networks in a resource-constrained environment. Spintronics is a prominent technology among emerging fields for next-generation on-chip non-volatile memory. Spin transfer torque (STT) and spin-orbit torque (SOT) based magnetic random-access memory (MRAM) offer non-volatility and negligible static power. Over the last few years, STT and SOT-based multilevel spintronic memories have emerged as a promising solution to attain high storage density. This paper presents the operation principle and performance evaluation of spintronics-based single-bit STT and SOT MRAM, dual-level cells, three-level cells (TLCs), and four-level cells. Further, multi-layer perceptron architectures have been utilized to perform MNIST image classification with these multilevel devices. The performance of the complete system level consisting of crossbar arrays with various MRAM bit cells in terms of area, energy, and latency is evaluated. The throughput efficiency of the BNN accelerator using TLCs is 26.6X, and 3.61X higher than conventional single-bit STT-MRAM, and SOT-MRAM respectively.

Spin orbit magnetic random access memory based binary CNN in-memory accelerator (BIMA) with sense amplifier

The research tends to suggest a spin-orbit torque magnetic random access memory (SOT-MRAM)-based Binary CNN In-Memory Accelerator (BIMA) to minimize power utilization and suggests an In-Memory Computing (IMC) for AdderNet-based BIMA to further enhance performance by fully utilizing the benefits of IMC as well as a low current consumption configuration employing SOT-MRAM. And recommended an IMC-friendly computation pipeline for AdderNet convolution at the algorithm level. Additionally, the suggested sense amplifier is not only capable of the addition operation but also typical Boolean operations including subtraction etc. The architecture suggested in this research consumes less power than its spin-orbit torque (STT) MRAM and resistive random access memory (ReRAM)-based counterparts in the Modified National Institute of Standards and Technology (MNIST) data set, according to simulation results. Based to evaluation outcomes, the pre-sented strategy outperforms the in-memory accelerator in terms of speedup and energy efficiency by 17.13× and 18.20×, respectively.

Advanced hybrid MRAM based novel GPU cache system for graphic processing with high efficiency

With the rapid development of portable computing devices and users’ demand for high-quality graphics rendering, embedded Graphics Processing Units (GPU) systems for graphics processing are increasingly turning into a key component of computer architecture to enhance computability. The cache system based on traditional static random access memory (SRAM) plays a crucial role in GPUs. But high leakage, low lifetime and poor integration problems deeply plague the science and engineering field. In the paper, a novel magnetic random access memory (MRAM) based cache architecture of GPU systems is proposed for highly efficient graphics processing and computing accelerating, with the merits of high speed, long endurance, strong interference resistance, and ultra-low power consumption. Spin transfer torque-MRAM and spin orbit torque-MRAM are utilized in off-chip and on-chip caches, respectively. A controller design scheme with prefetching modules and optimized cache coherency protocols are adopted. After testing and evaluating with multiple loads, neural network models and datasets, the simulation results show that the proposed system can achieve up to 28%, 56%, and 66.45% optimizations mostly in terms of speed, energy and leakage power, respectively.

Spin device-based image edge detection architecture for neuromorphic computing

Artificial intelligence and deep learning today are utilized for several applications namely image processing, smart surveillance, edge computing, and so on. The hardware implementation of such applications has been a matter of concern due to huge area and energy requirements. The concept of computing in-memory and the use of non-volatile memory (NVM) devices have paved a path for resource-efficient hardware implementation. We propose a dual-level spin–orbit torque magnetic random-access memory (SOT-DLC MRAM) based crossbar array design for image edge detection. The presented in-memory edge detection algorithm framework provides spin-based crossbar designs that can intrinsically perform image edge detection in an energy-efficient manner. The simulation results are scaled down in energy consumption for data transfer by a factor of 8x for grayscale images with a comparatively smaller crossbar than an equivalent CMOS design. DLC SOT-MRAM outperforms CMOS-based hardware implementation in several key aspects, offering 1.53x greater area efficiency, 14.24x lower leakage power dissipation, and 3.63x improved energy efficiency. Additionally, when compared to conventional spin transfer torque (STT-MRAM and SOT-MRAM, SOT-DLC MRAM achieves higher energy efficiency with a 1.07x and 1.03x advantage, respectively. Further, we extended the image edge extraction framework to spiking domain where ant colony optimization (ACO) algorithm is implemented. The mathematical analysis is presented for mapping of conductance matrix of the crossbar during edge detection with an improved area and energy efficiency at hardware implementation. The pixel accuracy of edge-detected image from ACO is 4.9% and 3.72% higher than conventional Sobel and Canny based edge-detection.

Spin Hall Switching Enabled by Uniaxial In-Plane Magnetocrystalline Anisotropy

We present a new method for stabilization of magnetic devices: in-plane uniaxial magnetocrystalline anisotropy, achieved through epitaxial growth of a magnetic thin film on a single-crystal substrate. This paradigm enables the creation of in-plane spin orbit torque magnetic random access memory (SOT-MRAM) devices that function without external fields and exhibit the same scalability as perpendicular SOT-MRAM. Through theoretical derivations and numerical simulations based on the Landau-Lifshitz-Gilbert (LLG) equation with spin transfer torque, we show that switching of such devices can be optimized by varying the angle between the injected spin current and the crystalline easy axis, and contrast this angular dependence with the Stoner-Wohlfarth model. Furthermore, we demonstrate rich and complex magnetization dynamics in this system, including strong and tunable dependence on bulk and interfacial magnetoresistance and boundaries between stochastic and deterministic switching. Finally, we present a concept that couples our in-plane anisotropy layer with an out-of-plane ferromagnet to achieve out-of-plane field-free SOT-MRAM switching. We quantify regions of operation for this new device and link them to simulation results for the in-plane layer alone.

Field-free magnetization switching through modulation of zero-field spin–orbit torque efficacy

To make spin–orbit torque magnetic random access memory (SOT-MRAM) practical, current-induced magnetization switching without an external bias field is essential. Given that the CoFeB/MgO structure has already been used in typical spin-transfer torque-MRAM for its high tunneling magnetoresistance, leveraging a similar material system to achieve field-free SOT switching is of great importance. In this work, we systematically investigate the field-free switching mechanism in CoFeB/W/CoFeB T-type structures, where the two CoFeB layers are in-plane and perpendicularly magnetized, respectively. Initial SOT characterization shows a sizable zero-field SOT efficacy (χHx=0) for such T-type devices. Furthermore, field-free angle-dependent SOT measurement confirms the parallel relationship between the built-in bias field and the magnetization of the in-plane magnetized CoFeB. Based on thorough verification and exclusion of other potential mechanisms, the Néel orange-peel effect emerges as the dominant origin for such a built-in bias field, where a positive correlation between the deposited film surface roughness and χHx=0 is found. Based on this discovery, the field-free switching efficacy in T-type structures is further optimized via film roughness tuning and examined with pillar-shaped devices. Our results provide insights into the tentative approach to improve field-free switching using T-type devices and the feasibility of downscaling.

High radiation tolerant SOT-MRAM read peripheral circuit with fast data recovery

With downscaling of process technology, single event upsets (SEUs) induced by radiation particles are becoming an important threat to the reliability of memories. Particularly, the charge sharing effect is more significant, causing multiple node upsets due to a single event. Spintronic memory is a viable contender for addressing this challenge, since magnetic tunnel junction (MTJ), the core component of spintronic memory, has been shown to be intrinsically immune to radiation effects. However, hybrid spintronic/CMOS peripheral circuits are still vulnerable to radiation effects. This paper proposes a novel radiation-hardened read circuit with recovery time and radiation tolerance optimized for spin–orbit torque magnetic random access memory (SOT-MRAM). The obtained results show that the proposed circuit can be highly resilient to SEUs independent of its polarity. It can tolerate 8.06X, 10.41X, 9.8X, and 3.49X more critical charge as compared to the 13T, 11T, 11T, and CMOS cross-coupled transistor radiation hardened circuits, respectively with some area overhead. Moreover, the proposed circuit has the least recovery time compared to the previously reported radiation hardened MRAM cell.

Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.

Low Energy and Write-Efficient Spin-Orbit Torque-Based Triple-Level Cell MRAM

Multi-level cell (MLC) is an attractive method to increase the memory storage density and reduce the cost per bit. Write disturb rate (WDR) and large writing step counts are the main challenge to implementing MLCs. In this paper, a three-bit spin-orbit torque magnetic random-access memory (SOT-MRAM) based MLC structure named TLC is proposed. The majority of the bits in TLC require two steps of writing for storage, and the cell exhibits WDR less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> . The performance evaluation of the proposed structure is done on the SPICE framework utilizing a Verilog-A model for the structure. The proposed TLC device is 96% and 92% more energy efficient than spin transfer torque (STT) based TLC and STT/SOT-based TLC structures, respectively. The worst-case write latency of the proposed TLC is 2ns that shows 88% improvement compared to the recently published STT/SOT-based TLC-MRAM. The variability analysis performed using Monte Carlo simulations shows sufficient margins between various writing currents employed for switching the stacked magnetic tunnel junctions (MTJs) that signifies the reliable switching of the different bits in the TLC.

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

Annealing effect on the magneto-electric properties of SOT-MTJs from micro to nano-sized dimensions

Spin–orbit torque magnetic random-access memory exhibits great potential for next-generation memory. Annealing is an essential process for SOT magnetic tunnel junctions (SOT-MTJs) thin films. To optimize the SOT-MTJ thin films, studying the different dimensions from micro-size to nano-size is very necessary. Here, we investigate the annealing effect on magneto-electric properties of micro-scaled and nano-scaled SOT-MTJs. The tunnel magnetoresistance (TMR) and critical current density (J c) increase after annealing, attributing to the improved crystallization of CoFeB layers and perpendicular magnetic anisotropy (PMA), respectively. However, the TMR increment of micro-scaled SOT-MTJ is larger than that in nano-scale, due to the reduced defects of micro-scaled SOT-MTJs by annealing. Additionally, the J c of nano-scaled SOT-MTJ is decoupled from that of micro-scaled SOT-MTJ because of the improved PMA and diminished thermal effect. This work assesses the different annealing effects in micro- and nano-sized dimensions and supplies experiment foundations to optimize the performance of SOT-MTJs.

Area and Energy Efficient SOT-MRAM Bit Cell Based on 3 Transistors With Shared Diffusion Regions

In this paper, we present a novel bit cell structure of spin-orbit-torque magnetic random access memory (SOT-MRAM) for the reduction of both cell size and write energy consumption. Based on the shared diffusion region architecture, all of the 3 transistors in one SOT-MRAM bit cell contribute to supply driving current for deterministic write operations. Implemented with a 40 nm CMOS technology, the proposed design achieves cell area reduction of 32% compared to conventional 2-transistors-based bit cell design from the simulation result. In addition, word-line voltage for access transistors in both designs are optimized and compared. Write energy of the proposed bit cell decreases with proper word-line voltage of the access transistors, reaching 80% (92%) write-P (AP) of the conventional cell design. Both the cell size scaling and energy saving make the proposed bit cell a viable design for high density and energy efficient SOT-MRAM.

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

This brief proposes a compact spin-orbit torque magnetic random-access memory (SOT-MRAM) cell structure with high read performance for embedded nonvolatile memory (eNVM) applications. The memory cell is composed of one transistor, two Schottky diodes, two magnetic tunnel junctions (MTJs) and one shared heavy metal (HM) layer, which can be abbreviated as 1T-2D-2MTJ cell. The two MTJs are stacked on the same HM layer for smaller area overhead and configured to be complementary with the magnetization of their pinned layers in the opposite direction to double the read sense margin. The write operation is also simplified since a current through the HM layer changes the resistances of both MTJs simultaneously. The evaluations include the micromagnetic simulation of the SOT device, the analysis of PVT variations for the read operation on bit-cell level, the estimation of bit-cell area and the simulations of performance and power consumption on array level. The results show that the proposed SOT-MRAM improves the performance and reliability of the read operation and achieves 75% (50%) reduction in bit-cell area compared to 4T-2MTJ SOT-MRAM (2T-2MTJ STT-MRAM), 83.0% reduction in write power consumption and 91.1% reduction in write latency compared to 2T-2MTJ STT-MRAM.

Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process

The emerging spin-orbit torque magnetic random-access memory (SOT-MRAM) shows promising prospects in high-level cache applications due to its sub-nanosecond switching speed and high reliability. However, SOT-MRAM faces the issue of large bit-cell layout area, which is currently the focus of attention. Although many design and evaluation works have emerged, the lack of a unified standard for realistic SOT process has hindered the development of relevant research towards practicality. In this paper, the bit-cell area of the SOT-MRAM will be evaluated and optimized based on the technically-feasible process. First of all, based on the state-of-the-art top-pinned SOT nanopillar process, the SOT-MRAM design rules are proposed. On this basis, this paper systematically summarizes four basic device layout modes and provides optimized layout suggestions for conventional SOT bit-cells with different types and sizes of devices. In addition, a series of area-efficient SOT bit-cell designs based on the common area (CA) and dual common (DC) solutions are proposed, which can reduce the layout area of SOT bit-cells by up to 38.4% with reasonable write latency and energy overhead.

Micromagnetic simulations for deterministic switching in SOT-MRAM cell with additional heavy metal capping strip

Spin–orbit torque magnetic random-access memory (SOT-MRAM) has received extensive interest in the memory industry. Recent works have focused on a heavy metal (HM)/ferromagnet bilayer with an additional HM capping strip to deterministically switch the magnetization. This paper investigates the switching behaviors of SOT-MRAM utilizing this structure with micromagnetic simulations coupled to the drift-diffusion spin transport model. The mechanism is attributed to the non-negligible negative z-component from spin accumulation on the bottom HM interface, which originates from the associated accumulation at the edges of the HM capping strip. Moreover, device parameters are shown as crucial for deterministic switching and lower power consumption. This study provides fundamental insights into deterministic switching for SOT-MRAM with an additional HM capping strip, which can be readily adopted into practical applications.

Voltage-Controlled Dzyaloshinskii-Moriya Interaction Torque Switching of Perpendicular Magnetization.

Magnetization switching is the most important operation in spintronic devices. In modern nonvolatile magnetic random-access memory (MRAM), it is usually realized by spin-transfer torque (STT) or spin-orbit torque (SOT). However, both STT and SOT MRAM require current to drive magnetization switching, which will cause Joule heating. Here, we report an alternative mechanism, Dzyaloshinskii-Moriya interaction (DMI) torque, that can realize magnetization switching fully controlled by voltage pulses. We find that a consequential voltage-controlled reversal of DMI chirality in multiferroics can lead to continued expansion of a skyrmion thanks to the DMI torque. Enough DMI torque will eventually make the skyrmion burst into a quasiuniform ferromagnetic state with reversed magnetization, thus realizing the switching of a perpendicular magnet. The discovery is demonstrated in two-dimensional multiferroics, CuCrP_{2}Se_{6} and CrN, using first-principles calculations and micromagnetic simulations. As an example, we applied the DMI torque for simulating leaky-integrate-fire functionality of biological neurons. Our discovery of DMI torque switching of perpendicular magnetization provides tremendous potential toward magnetic-field-free and current-free spintronic devices, and neuromorphic computing as well.

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.