Voltage Spikes Research Articles

Development and Implementation of a RC Snubber to Suppress Breaker Arcing Present in High-Stored-Energy Superconducting Magnet Systems

Arc suppression Snubbers offer safety in high energy superconducting magnet systems. Large superconducting magnets may have arcing across their breakers at the moment of slow dump initiation resulting from a sudden current redistribution in the powering circuit. The ATLAS Experiment at CERN experiences such arcing with its 7.3 H Toroidal magnet powering circuit. To discharge the magnets, the current is redistributed to a parallel branch called the Run Down Unit (RDU) by means of a breaker. Due to the physical layout and other metallic components in the vicinity, the power supply and RDU branches have undesirable and unavoidable parasitic inductance, causing a voltage spike over the main breakers at the moment of opening. The resulting arcing deteriorates the breaker contacts, resulting in increased operating temperatures and a more frequent need for maintenance. The arc suppression system developed takes the form of an RC Snubber (Resistor-Capacitor). The Snubber offers the current a low-impedance path, thus smoothing out the current redistribution and suppressing the voltage spike. This initial charging period of the capacitors gives the current enough time to overcome the parasitic inductance, therefore allowing the RDU to smoothly ramp up without a sudden voltage spike. To test the concept, a 1/50th scale demonstrator was developed and showed successful results. After the demonstrator, endurance testing of the electrolytic capacitors was performed to ensure no degradation of the charging characteristics for an equivalent of 20 years of operation. The Snubber was manufactured and implemented with successful results on the ATLAS Toroidal powering circuit.

Changes in illegal fishing dynamics in a large-scale MPA during COVID-19

Global socio-ecological shocks, such as the COVID-19 pandemic, can threaten progress in protecting vulnerable marine environments by altering behaviour of resource users1. When government priorities shift from environmental protection towards safeguarding human populations, control of illegal activity in protected areas can alter. Resulting increases in illegal fishing in large-scale marine protected areas (MPAs) are of particular concern as they contain a large proportion of marine protected area globally2. Here, we report on average 19 times as many suspected illegal fishing vessels per month in 2022 (n = 19) compared with 2010 to 2020 (n = 1) in an Indian Ocean MPA. Although illegal fishing has been a pervasive problem, the current spike in Indian vessels targeting a broad trophic diversity of reef-associated species is of particular concern and we suggest such changes in illegal activity in MPAs globally may persist over long timescales unless management is broad and adaptive to individual context. When considering potential solutions, widespread adoption of technology, such as remote surveillance of vessels, can mitigate illegal activities but remains unfeasible for many MPAs globally due to financial and political barriers. Instead, we suggest broader approaches, including a renewed focus on regional approaches to combating illegal fishing, formal bilateral agreements between competent authorities in relevant countries and an increase in community-based work.

ECoG spiking activity and signal dimension are early predictive measures of epileptogenesis in a translational mouse model of traumatic brain injury

The latency between traumatic brain injury (TBI) and the onset of epilepsy (PTE) represents an opportunity for counteracting epileptogenesis. Antiepileptogenesis trials are hampered by the lack of sensitive biomarkers that allow to enrich patient's population at-risk for PTE. We aimed to assess whether specific ECoG signals predict PTE in a clinically relevant mouse model with ∼60% epilepsy incidence. TBI was provoked in adult CD1 male mice by controlled cortical impact on the left parieto-temporal cortex, then mice were implanted with two perilesional cortical screw electrodes and two similar electrodes in the hemisphere contralateral to the lesion site. Acute seizures and spikes/sharp waves were ECoG-recorded during 1 week post-TBI. These early ECoG events were analyzed according to PTE incidence as assessed by measuring spontaneous recurrent seizures (SRS) at 5 months post-TBI. We found that incidence, number and duration of acute seizures during 3 days post-TBI were similar in PTE mice and mice not developing epilepsy (No SRS mice). Control mice with cortical electrodes (naïve, n = 5) or with electrodes and craniotomy (sham, n = 5) exhibited acute seizures but did not develop epilepsy. The daily number of spikes/sharp waves at the perilesional electrodes was increased similarly in PTE (n = 15) and No SRS (n = 8) mice vs controls (p < 0.05, n = 10) from day 2 post-injury. Differently, the daily number of spikes/sharp waves at both contralateral electrodes showed a progressive increase in PTE mice vs No SRS and control mice. In particular, spikes number was higher in PTE vs No SRS mice (p < 0.05) at 6 and 7 days post-TBI, and this measure predicted epilepsy development with high accuracy (AUC = 0.77, p = 0.03; CI 0.5830–0.9670). The cut-off value was validated in an independent cohort of TBI mice (n = 12). The daily spike number at the contralateral electrodes showed a circadian distribution in PTE mice which was not observed in No SRS mice. Analysis of non-linear dynamics at each electrode site showed changes in dimensionality during 4 days post-TBI. This measure yielded the best discrimination between PTE and No SRS mice (p < 0.01) at the cortical electrodes contralateral to injury. Data show that epileptiform activity contralateral to the lesion site has the the highest predictive value for PTE in this model reinforcing the hypothesis that the hemisphere contralateral to the lesion core may drive epileptogenic networks after TBI.

A Novel Three-Winding Coupled Inductor-Based High Step-Up DC-DC Converter for Renewable Energy Application

This paper presents a novel nonisolated high step-up dc-dc converter for renewable energy generation system. The converter combines a three-winding coupled inductor, voltage multiplier cells, and two power switches with simultaneous operation. Compared with existing high step-up converters, the proposed converter can achieve high voltage gain under a low number of turns ratio while avoiding a large duty cycle. Moreover, the passive clamp circuit recycles leakage inductor energy and reduces the voltage spike of switches. Continuity of input current and existence of a common ground between the input energy source and load make the converter suitable for renewable energy applications. Also, the proposed converter shares high voltage gain with low voltage stress on semiconductors (switches/diodes), improved compactness and high efficiency. The operating principles and steady-state analysis of the proposed converter are illustrated. Then the theoretical efficiency analysis, and performance comparison with other converters are discussed. Finally, a 200 W prototype with 380 V output voltage is established based on the design guidelines, and experimental results verify the accuracy of the theoretical analysis.

Three-Port Converter With Leakage Inductance Energy Recycling for High Step-Down Applications

An emerging revolution in electric vehicles (EVs) is rapidly taking over the traditional fossil fuel vehicle market. Given its safety features and user-friendliness, the dual battery system (DBS) has been adopted in various EVs. A step-down three-port converter is essential for the DBS to supply low-voltage auxiliary power in EVs. In this paper, a novel high step-down three-port converter (TPC) is proposed by integrating the tapped-inductor technique and a buck converter for fulfilling the requirements of high step-down power conversion from sources to load with a reasonable duty cycle. It can also achieve independent power transfer among three ports. In addition, the energy stored in the leakage inductance of coupled inductor is recycled, with voltage spikes reduced across the switches. Finally, an experimental prototype is built to verify the theoretical analysis, with a main battery of 300 V, auxiliary battery of 48 V, load voltage of 24 V, and rated power of 300 W. The highest efficiency reached is 96.6%.

A novel control method for enhanced performance of single‐phase matrix converters

AbstractThe conventional topology of direct single‐to‐single‐phase matrix converter (SSMC) is widely adopted in industrial and power system‐related applications owing to its desired features. Current control methods in the literature either limit the voltage transfer ratio (VTR) or prohibit their utilization to drive inductive (RL) loads. In this study, we propose a novel control method that overcomes these limitations by enabling the SSMC to achieve relatively high VTRs while driving RL loads with negligible output voltage spikes and without current commutation problems. Further, the proposed control method improves the overall performance by reducing output voltage and source input current total harmonic distortion (THD) and offering soft‐switching at the commutation instances. The rigidity of the proposed control method over the counterpart methods in the literature is verified through simulation and experimental case studies over a wide range of synthesized output frequencies and modulation indexes. A 530‐W laboratory prototype is built for the experimental study. Results demonstrated the ability of the proposed method in enabling the SSMC to drive an RL load without current commutation issues and with mitigated output voltage spikes while achieving relatively high VTRs and suppressing the output voltage and source input current THD.

Enhanced plasma current spike formation due to onset of 1/1 kink-tearing reconnection during a massive gas injection process

The formation of the plasma current spike at the end of the thermal quench (TQ) phase is studied systematically, which is found to strongly correlate with the onset of the 1/1 kink-tearing reconnection only in the simulation results presented here. The magnetohydrodynamic activity on the q = 1 surface plays a critical role in the spike formation and the disruption process. In particular, when the safety factor in the magnetic axis q0 exceeds 1, the plasma major disruption transits into successive minor disruptions, and the start of the TQ phase is delayed.

High Step-Up Current-Fed Diode-Clamped Resonant Converter for Overloaded Fuel-Cell Vehicles

We propose a high step-up current-fed diode-clamped resonant converter for overloaded fuel-cell vehicles. The electric motor is able to demand short-time peak torque during sudden acceleration phase or long-time excessive torque when the fuel-cell vehicles are overloaded. Then, the conventional converter suffers from a high current spike at the secondary-side switches. The proposed converter incorporates diode-clamped cell on the secondary side, and therefore does not have the high current spike, but retains the benefits of the conventional converter such as high step-up function, ripple-free characteristic, and soft switching capability. When the output power is over its maximum nominal value, the secondary-side switches are switched off with complete zero-voltage-switching (ZVS) and the secondary-side diodes are off with zero-current-switching (ZCS). As a result, the proposed converter exhibits high efficiency and long-term operation under the nominal power and even at peak power. Furthermore, we have analyzed voltage gain, ZVS/ZCS region, and current/voltage stress on the active power components when the output power is over its maximum nominal value, which is different from those when the output power is in its nominal range. The theoretical analysis of the proposed converter is presented, then validated using a laboratory-built prototype.

Design and implementation of a cost-efficient clamping capacitor boost converter for a hybrid renewable energy system for increased gain to fulfil demands

Power generation plants are built in rural areas to meet the power demands and empower the financial status. The existing method of electrical power generation is difficult to meet the growing population as they are turning to hybrid renewable energy systems to meet the increasing demand. They were also not focused on power saving and flow with reduced power loss. The power generated from hybrid renewable energy systems is distributed to rural areas through a DC-DC converter. The DC-DC converter converts the Hybrid Renewable Energy System (HRE) output into a high DC voltage transmitted in a bus. The proposed HRE system consists of solar and wind plants in the network. So, for transferring, saving, and utilizing the power generated from the hybrid renewable energy system, a cost-efficient clamping capacitor boost converter (CCBC) with increased voltage gain is proposed. The CCBC has a clamping capacitor in-built with 2-diodes and 2-capacitors. The voltage gain produced using the proposed CCBC is doubled with the conventional converters. There is no high range of power spikes in the converter's capacitor. This paper explains the architecture and the complete functionality of the CCBC with the simulation results in detail. The simulation results conclude that the proposed CCBC provides cost-efficient high voltage gain converters for HRE systems, providing more than 500 W, which fulfills the demand of a single rural area.

A Novel DC Electronic Load Topology Incorporated with Model Predictive Control Approach

This paper presents a novel topology of a modified isolated single-ended-primary-inductance converter (SEPIC) with a model predictive control (MPC) approach applied to direct current (DC) electronic loads. The proposed converter uses an actual transformer rather than a coupled inductor for isolation between the source and the load. The transformer allows the proposed converter to operate at a higher switching frequency, ultimately reducing the passive components’ size. A low-power hardware prototype is developed and tested with a model predictive control algorithm under variable input voltages and load conditions. The performance of the proposed converter is demonstrated to be satisfactory under steady state, as well as sudden input voltage transients. The proposed converter utilizes a switched capacitor technique to generate alternating current in both windings of the transformer. As the coupled inductor is eliminated from the circuit, the problem of high voltage spikes occurring due to leakage inductances is also eliminated for the proposed converter. Therefore, the proposed converter can be used for isolated medium power applications. The experimental results show that the efficiency of the proposed converter reached 96%. The MPC allows this converter’s DC voltage level to remain stable even as the input voltage and output terminal load change. Lastly, this converter with an MPC approach can be applied to different DC electronic loads, improving DC power quality and DC electronic load life.

Reducing Surge Voltage and Ringing Effect of DC Voltage Converter by Transient Suppressor

Reducing Surge Voltage and Ringing Effect of DC Voltage Converter by Transient Suppressor

Performing Arithmetic Operations with Locally Homogeneous Spiking Neural P Systems

The parallelism of rule execution in membrane computing provides support for improving computational efficiency. Membrane computing models have been applied in many fields. In arithmetic operations, designing basic arithmetic operation spiking neural P systems using fewer neurons and rule types has been an important field of membrane computing application research in recent years. We discuss the application of locally homogeneous spiking neural P systems in arithmetic operations. The purpose is to design a spiking neural P system with fewer neurons and rule types to perform arithmetic operations. We designed the addition and subtraction of a locally homogeneous spiking neural P system without weight and delay. They include two input neurons to achieve any two binary number subtraction, one input neuron to achieve any two binary number addition and subtraction, and one input neuron to achieve any n binary number addition and subtraction. This is an attempt to apply the locally homogeneous spiking neural P system in arithmetic operations. Compared with the current excellent spiking neural P system performing arithmetic operations, our designed locally homogeneous spiking neural P system is more concise. The system we designed reduces the number of neurons required for n number addition operations by k − 6 and reduces the number of rule types by 5k − 14.

Excitatory nucleo-olivary pathway shapes cerebellar outputs for motor control

The brain generates predictive motor commands to control the spatiotemporal precision of high-velocity movements. Yet, how the brain organizes automated internal feedback to coordinate the kinematics of such fast movements is unclear. Here we unveil a unique nucleo-olivary loop in the cerebellum and its involvement in coordinating high-velocity movements. Activating the excitatory nucleo-olivary pathway induces well-timed internal feedback complex spike signals in Purkinje cells to shape cerebellar outputs. Anatomical tracing reveals extensive axonal collaterals from the excitatory nucleo-olivary neurons to downstream motor regions, supporting integration of motor output and internal feedback signals within the cerebellum. This pathway directly drives saccades and head movements with a converging direction, while curtailing their amplitude and velocity via the powerful internal feedback mechanism. Our finding challenges the long-standing dogma that the cerebellum inhibits the inferior olivary pathway and provides a new circuit mechanism for the cerebellar control of high-velocity movements.

Designing a Smart Inverter for Compensating the Voltage Sag Caused by Motor Start-up

Starting a large induction motor will always follow up with an inrush current as the nature of an induction motor. On a less stiff power system, that inrush current will be causing a Voltage Sag (VS). A big VS can lead to significant disruptions in power quality and reliability. To address this, a Smart Inverter with an Artificial Intelligence (AI) -driven controller installed in a Photovoltaic (PV) farm is proposed for voltage sag recovery. During normal conditions, the PV farm acts as a power source supporting the main grid, but when large induction motors are started, the smart inverter connected to the PV is responsible for power conversion to recover sags caused by the Induction motor inrush current. The controller inside the Inverter ensures optimal operation. The use of AI also compares the effectiveness of using the Fuzzy Logic Controller (FLC) with the Proportional Integral (PI) Controller to assess their performance in reducing current spikes. Based on simulations, the FLC outperformed PI Controller in mitigating the voltage sag and avoiding the Low Voltage Ride-Through (LVRT). Simulation results show that voltage sag can be recovered for up to 97% of the nominal voltage, a significant improvement over the 80% sag recovery without the smart Inverter. At a nominal grid voltage of 6,600 volts, the VS Magnitude was successfully increased from 5,210 volts to 6,368 volts and the VS Duration also decreased from 6.96 s to 4.97 s. The results achieved validate the effectiveness of the approach in improving the power quality.

Brain-inspired nanophotonic spike computing: challenges and prospects

Nanophotonic spiking neural networks (SNNs) based on neuron-like excitable subwavelength (submicrometre) devices are of key importance for realizing brain-inspired, power-efficient artificial intelligence (AI) systems with high degree of parallelism and energy efficiency. Despite significant advances in neuromorphic photonics, compact and efficient nanophotonic elements for spiking signal emission and detection, as required for spike-based computation, remain largely unexplored. In this invited perspective, we outline the main challenges, early achievements, and opportunities toward a key-enabling photonic neuro-architecture using III–V/Si integrated spiking nodes based on nanoscale resonant tunnelling diodes (nanoRTDs) with folded negative differential resistance. We utilize nanoRTDs as nonlinear artificial neurons capable of spiking at high-speeds. We discuss the prospects for monolithic integration of nanoRTDs with nanoscale light-emitting diodes and nanolaser diodes, and nanophotodetectors to realize neuron emitter and receiver spiking nodes, respectively. Such layout would have a small footprint, fast operation, and low power consumption, all key requirements for efficient nano-optoelectronic spiking operation. We discuss how silicon photonics interconnects, integrated photorefractive interconnects, and 3D waveguide polymeric interconnections can be used for interconnecting the emitter-receiver spiking photonic neural nodes. Finally, using numerical simulations of artificial neuron models, we present spike-based spatio-temporal learning methods for applications in relevant AI-based functional tasks, such as image pattern recognition, edge detection, and SNNs for inference and learning. Future developments in neuromorphic spiking photonic nanocircuits, as outlined here, will significantly boost the processing and transmission capabilities of next-generation nanophotonic spike-based neuromorphic architectures for energy-efficient AI applications. This perspective paper is a result of the European Union funded research project ChipAI in the frame of the Horizon 2020 Future and Emerging Technologies Open programme.

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

AbstractWith continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

An improved high-accuracy interpolation method for switching devices in EMT simulation programs

This paper presents an interpolation with Backward Euler (BE) method that enhances the switching simulations accuracy in an electromagnetic transient (EMT) simulation with a fixed time-step. Because of the switching operations on discrete instants, the simulations can show artificial voltage spikes and numerical oscillations (chatter), compromising the accuracy and producing misleading results. We thus present a method that eliminates the spurious switching losses and improves the accuracy by combining interpolation and extrapolation with a half-time-step BE solution over existing interpolation-based approaches to resolve the issues above. In addition, this improved method requires the same calculation steps as the industry-accepted instantaneous interpolation. Analytical discussion reinforced by the simulation studies for a simple and complex power electronic circuits demonstrates the accuracy and efficacy of the proposed interpolation with BE method.

Core processing neuron‐enabled circuit motifs for neuromorphic computing

AbstractBased on brain‐inspired computing frameworks, neuromorphic systems implement large‐scale neural networks in hardware. Although rapid advances have been made in the development of artificial neurons and synapses in recent years, further research is beyond these individual components and focuses on neuronal circuit motifs with specialized excitatory–inhibitory (E–I) connectivity patterns. In this study, we demonstrate a core processor that can be used to construct commonly used neuronal circuits. The neuron, featuring an ultracompact physical configuration, integrates a volatile threshold switch with a gate‐modulated two‐dimensional (2D) MoS2 field‐effect channel to process complex E–I spatiotemporal spiking signals. Consequently, basic neuronal circuits are constructed for biorealistic neuromorphic computing. For practical applications, an algorithm‐hardware co‐design is implemented in a gate‐controlled spiking neural network with substantial performance improvement in human speech separation.image

Analysis and Measurement of the Surge and Gate-Noise Voltages in a 1.7-kV IGBT Module With the Effect of Reverse-Recovery Current

This paper reveals the effect of the reverse-recovery current of a PIN diode on the surge and gate-noise voltage of an insulated-gate bipolar transistor (IGBT) in an inverter. Theoretical analysis reveals that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$di/dt$</tex-math></inline-formula> of the reverse-recovery current, the switching speed of the IGBT and parasitic inductances affect the gate-noise voltage unlike a Schottky barrier diode (SBD) because resonance does not occur due to junction capacitances. The analysis also indicates that the surge voltage may not occur when the dc voltage is increased even though a large amount of surge voltage occurs in a low dc voltage region. A 1-kV testing setup was designed and constructed using a 1.7-kV 260-A IGBT module, which confirms the validity of the theoretical analysis.

A positively tuned voltage indicator for extended electrical recordings in the brain.

Genetically encoded voltage indicators (GEVIs) enable optical recording of electrical signals in the brain, providing subthreshold sensitivity and temporal resolution not possible with calcium indicators. However, one- and two-photon voltage imaging over prolonged periods with the same GEVI has not yet been demonstrated. Here, we report engineering of ASAP family GEVIs to enhance photostability by inversion of the fluorescence-voltage relationship. Two of the resulting GEVIs, ASAP4b and ASAP4e, respond to 100-mV depolarizations with ≥180% fluorescence increases, compared with the 50% fluorescence decrease of the parental ASAP3. With standard microscopy equipment, ASAP4e enables single-trial detection of spikes in mice over the course of minutes. Unlike GEVIs previously used for one-photon voltage recordings, ASAP4b and ASAP4e also perform well under two-photon illumination. By imaging voltage and calcium simultaneously, we show that ASAP4b and ASAP4e can identify place cells and detect voltage spikes with better temporal resolution than commonly used calcium indicators. Thus, ASAP4b and ASAP4e extend the capabilities of voltage imaging to standard one- and two-photon microscopes while improving the duration of voltage recordings.