Spike Rapid Thermal Annealing Research Articles

Study of phosphorus doped Si:C films formed by in situ doped Si epitaxy and implantation process for n-type metal-oxide-semiconductor devices

The effect of cluster carbon implantation and recrystallization on properties of phosphorus doped Si (Si:P) epitaxial films was investigated. Recrystallization techniques based on solid phase epitaxy with rapid thermal annealing (RTA), spike RTA (sRTA), and millisecond laser annealing were employed. It was found that strained carbon doped Si:P (Si:CP) layers with high [C]sub can be achieved by using low temperature sRTA/RTA due to the suppression of carbon–phosphorus coclustering in Si. Additional laser annealing can activate the remaining “nonactive” P atoms in the Si:CP layer recrystallized at low temperatures such as 900 °C sRTA and 800 °C 5 s RTA. This approach of combining a low temperature recrystallization anneal with an additional high temperature laser anneal was found to be useful for creating Si:CP layers with good crystallinity, low resistivity, and less phosphorus diffusion. Finally, a tensile strain was confirmed to be induced into the transistor channel by implementing the recrystallization technique on three dimensional fin-shaped field effect transistor device structures. A high recrystallization temperature of 1025 °C sRTA was found to be required for achieving complete recrystallization and suppressing introduction of defects/stacking faults in a Si:CP source/drain region.

INVESTIGATION OF NEAR-SURFACE DEFECTS INDUCED BY SPIKE RAPID THERMAL ANNEALING IN c-SILICON SOLAR CELLS

The defects induced by a spike rapid thermal annealing (RTA) process in crystalline silicon (c-Si) solar cells were investigated by the photoluminescence (PL) technique and the transmission electron microscopy (TEM), respectively. Dislocation defects were found to form in the near-surface junction region of the monocrystalline Si solar cell after a spike RTA process was performed at 1100[Formula: see text]C. Photo J–V characteristics were measured on the Si solar cell before and after the spike RTA treatments to reveal the effects of defects on the Si cell performances. In addition, the Silvaco device simulation program was used to study the effects of defects density on the cell performances by fitting the experimental data of RTA-treated cells. The results demonstrate that there was an obvious degradation in the Si solar cell performances when the defect density after the spike RTA treatment was above [Formula: see text][Formula: see text]cm[Formula: see text].

Atomistic Modeling of Pocket Dopant Deactivation and Its Impact on <inline-formula> <tex-math notation="LaTeX">$V_{\textrm {th}}$ </tex-math></inline-formula> Variation in Scaled Si Planar Devices Using an Atomistic Kinetic Monte Carlo Approach

An analysis of pocket dopant deactivation and its impact on $V_{\textrm {th}}$ variation for scaled Si devices using an atomistic kinetic Monte Carlo approach are shown in this paper. B 5 keV, $5\times 10^{13}$ /cm $^{\mathrm {{2}}}+$ As 1 keV, $1 \times 10^{15}$ /cm $^{\mathrm {{2}}}$ implants were used for B pocket deactivation study. An effect of laser annealing (LA) before spike-Rapid Thermal Annealing (RTA) was investigated. In case of B pocket implant, a stable B cluster configuration is changed from $\text{B}_{\mathrm {{3}}}\text{I}$ (>1020 °C) to BI $_{\mathrm {{2}}}$ at spike-RTA temperature $\sim 1020^{\circ }\text{C}$ . BI $_{\mathrm {{2}}}$ is a source of B pocket deactivation with lower temperature than 1020 °C. LA before low-temperature spike-RTA ( $V_{\textrm {th}}$ mismatch figure of merit extracted from Pelgrom plot (Avt) degradation in nFET is shown as spike-RTA temperature is reduced. LA before spike-RTA shows a better short channel effect with lower drain-induced barrier lowering in nFET. LA + spike-RTA at 1000 °C shows better Avt than spike-RTA-only. The difference of pocket deactivation is one of possible important reasons for the higher $V_{\textrm {th}}$ mismatch for nFET than for pFET.

Formation of Si:CP layer through in-situ doping and implantation process for n-type metal–oxide–semiconductor devices

In this study, the effect of Cluster Carbon implantation and thermal annealing for recrystallization on the properties of phosphorus doped Si (Si:P) epitaxial films was investigated. Several Cluster Carbon implantation conditions and recrystallization annealing techniques based on solid phase epitaxy with rapid thermal annealing (RTA), spike RTA (sRTA), and millisecond laser annealing have been employed. It was found that a high substitutional carbon concentration can be achieved by laser annealing while high thermal budget annealing caused the loss of almost half of the substitutional carbon. The reduction of end of range defects and stacking faults/dislocation loops at the surface of carbon and phosphorus doped Si (Si:CP) layers through the use of cold implantation and fewer implantations was confirmed. Although sRTA activates phosphorus, additional laser annealing improves phosphorus activation further in the Si:CP layer. The phosphorus profile is abrupt with Cluster Carbon implantation when compared to no carbon implantation.

A unified interdiffusivity model and model verification for tensile and relaxed SiGe interdiffusion over the full germanium content range

An interdiffusivity model was established for SiGe interdiffusion under tensile or relaxed strain over the full Ge content (xGe) range (0 ≤ xGe ≤ 1), which is based on the correlations between self-diffusivity, intrinsic diffusivity, and interdiffusivity. It unifies available interdiffusivity models over the full Ge range and applies to a wider temperature range up to 1270 °C at the xGe = 0 end and to 900 °C at the high xGe = 1 end. Interdiffusion experiments under soak and spike rapid thermal annealing conditions were conducted to verify the model. Literature interdiffusion data under furnace annealing conditions were also used for the same purpose. The interdiffusivity model of this work has been implemented in major process simulation tools, and the simulation results showed good agreement with experimental data under furnace annealing and soak and spike rapid thermal annealing conditions. This work demonstrated a new approach in studying SiGe interdiffusion, which has the advantage of studying interdiffusion under non-isothermal annealing conditions.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Vacancy-Boron Complexes in Plasma Immersion Ion-Implanted Si Probed by a Monoenergetic Positron Beam

Vacancy-type defects in plasma immersion B-implanted Si were probed by a monoenergetic positron beam. Doppler broadening spectra of the annihilation radiation were measured and compared with spectra calculated using the projector augmented-wave method. For the as-doped sample, the vacancy-rich region was found to be localized at a depth of 0–10 nm, and the major defect species were determined to be divacancy–B complexes. After spike rapid thermal annealing at 1075 °C, the lineshape parameter S of Doppler broadening spectra corresponding to the high-B-concentration region (4–30 nm) was found to be smaller than the characteristic S value obtained for defect-free Si. From a detailed analysis of the Doppler broadening spectra, the origin of the decrease in the S value was attributed to the trapping of positrons by negatively charged B clusters such as icosahedral B12.

Alternating Reversed Scanning Sequence for Improved Within-Wafer Uniformity During Nonmelt Laser Annealing of Arsenic-Implanted Silicon

Beyond the 45-nm technology node, nonmelt laser thermal annealing (LTA) is a potential candidate to replace the spike rapid thermal annealing (RTA) for the formation of ultrashallow and highly activated source/drain extension junctions. However, one major drawback of LTA is that it is ineffective in the removal of implantation-induced damage. As such, arsenic deactivation, as a result of cluster formation due to the release of excess interstitials from the end-of-range (EOR) region, is observed when a post-LTA thermal budget is applied. Since conventional LTA comprises localized heating using a laser beam scanning the wafer front-side in a nonalternating sequence, different portions of the wafer will experience varying post-LTA thermal budget from the hotplate, depending on when the laser beam scans through it. Because dopant deactivation increases as the post-LTA thermal budget increases, severe degradation of the within-wafer uniformity is observed. To address this problem, a multiple-pulse, alternating reversed laser scanning technique is implemented to average out the differences in post-LTA thermal budget across the wafer between each pulse. Using such a scheme, the variations in subsequent dopant deactivation across the wafer is reduced and significant uniformity improvement of up to 50% is observed.

Influence of RTA and LTA on the Optical Propagation Loss in Polycrystalline Silicon Wire Waveguides

To provide flexibility in implementing polySi devices in Si optoelectronic integrated circuits, polySi wire waveguides were fabricated with various low thermal budget solid-phase crystallization (SPC) approaches, i.e., spike rapid thermal annealing (RTA) at 1050°C for < 1 s, low-temperature annealing (LTA) at 600°C for 15 h, or a combination of both with different sequences. The approach of first LTA and then RTA reaches a relatively low optical loss at 1550 nm: ~ 9.8 dB/cm in 300-nm-wide polySi waveguides after an additional forming gas annealing at 420°C to passivate the dangling bonds, close to that fabricated with the conventional high thermal budget SPC.

Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy

Junction depth and parasitic resistance have a trade-off relationship. To improve this relationship, in situ boron-doped selective Si epitaxy was used to fabricate metal–oxide–semiconductor field-effect transistors (MOSFETs) with raised source and drain extensions and a facet. The amount of boron diffusion was small and the MOSFET also had low extension sheet resistance. Furthermore, with the optimization of four process parameters, spike rapid thermal annealing (RTA) temperature, halo dose, impurity concentration introduced by in situ doping, and epitaxial Si thickness, the relationship between the gate length at Ioff=100 nA/µm and the drive current at Ioff=100 nA/µm was improved.

Pulsed Inductively-Coupled Plasma Doping of Phosphorus for N+-P Junction Fabrication

Plasma doping is an attractive technology that may be capable of producing ultra-shallow junctions with high productivity. We used a pulsed inductively-coupled plasma (ICP) to increase the plasma density and to reduce particulates and deposits. We doped phosphorus ions at a low substrate bias voltage (0.2 to 2 kV) by using PH3 as the process gas. An n+-p junction with low sheet resistance was then formed by spike rapid thermal annealing (RTA). We investigated the density of the pulsed plasma as a function of time to determine the optimal delay time for the substrate pulse bias after the RF power of the ICP antenna had been switched on. The pulse width of the substrate bias was optimized to 50 s to maximize the throughput. We compared the plasma doping with a traditional beam-line ion implantation and found that it resulted in a lower junction depth and a higher sheet resistance at the same voltage. A junction depth of 34 nm and a sheet resistance of 590 / were obtained by plasma doping at 0.5 kV with spike RTA at 950 C.

Minimizing Device Variation Caused by RTA Temperature Variation Across the Shot Field

Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the shot, a systematic study on STI and poly pattern density distribution across the shot field and their effects on the RTA temperature was carried out. It was demonstrated that the STI and poly pattern density variation across the field will result in more than 10ºC RTA temperature variation. To minimize the effect, an optimization of RTA ramp rate and peak temperature was studied. Source/drain (S/D) extension and S/D implant optimization has also been done for the reduction of PMOS device Idsat temperature sensitivity

Optimization of Stress Memorization Technique for 45 nm Complementary Metal–Oxide–Semiconductor Technology

The effect of stress memorization technique (SMT) on performance of transistors and power reduction is intensively studied. A 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously by choosing the appropriate stressor film with a large stress change by spike rapid thermal annealing (RTA). Stress distribution in the channel region for SMT is confirmed to be uniform; hence, the layout dependence is minimized and the performance is maximized in aggressively scaled complementary metal–oxide–semiconductor (CMOS) with dense gate pitch rule (190 nm) in 45 nm technology node.

Advanced activation trends for boron and arsenic by combinations of single, multiple flash anneals and spike rapid thermal annealing

Millisecond annealing as an equipment technology provides temperature profiles which favour dopant activation but nearly eliminate dopant diffusion to form extremely shallow, highly electrically activated junctions. For the 45-nm technology node and beyond, precisely controlled gate under-diffusion is required for optimum device performance. Therefore, on boron and arsenic beamline-implanted wafers, various annealing schemes were investigated for the formation of ultra-shallow and custom-shaped junctions. The main scheme consisted of flash annealing with peak temperatures ranging from 1250 to 1300 °C, combined with spike rapid thermal annealing with peak temperatures in the range from 900 to 1000 °C to achieve a desired junction depth. As alternative, to reduce the sheet resistance of pMOS and nMOS source–drain extensions, combinations of two or three flash anneals in succession were tested. Finally, the standard flash anneal condition of a 750 °C intermediate temperature followed by the flash anneal was changed to a high intermediate temperature of 950 °C followed by the flash anneal up to 1300 °C. The results of all these annealing schemes were analysed by four-point probe measurement. Selected samples were analysed by Hall-effect measurements for peak activation, and by secondary ion mass spectrometry for profile shape as well as diffusion effects. Transmission electron microscopy was used to study residual defects. Selected boron and arsenic dopant profiles were also compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.

Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- $k$ FETs

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> roll-offs and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> 's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

Effect of amorphization and carbon co-doping on activation and diffusion of boron in silicon

We investigate the impact of amorphization and C co-implantation on B diffusion and activation properties after conventional spike rapid thermal annealing (RTA). We observe that after complete recrystallization at 600°C the B tail deepens by 5nm (at 5×1018at.∕cm3) due to B diffusion in a-Si. After spike RTA it becomes 12nm deeper with respect to an as-implanted profile, which proves that both diffusion mechanisms in a-Si and c-Si are important. However, the B diffusion in c-Si is sensitive to the fraction of substitutional C incorporated into c-Si. The best junction depth is Xj=16.5nm, with abruptness of 2nm/decade and Rs=583Ω∕◻.

Suppression of phosphorus diffusion by carbon co-implantation

The impact of Si interstitial (Sii) flux suppression on the formation of P junctions by rapid thermal annealing (RTA) is demonstrated. Here we investigate the role of amorphization coupled with C co-implantation on P diffusion and its activation. From experiments on C co-implants in a-Si versus c-Si, we conclude that only a small fraction of C interacts with Si interstitials (Sii). We have demonstrated that optimization of implants followed by spike RTA yields extensions suitable for gate lengths of 30nm, with vertical depth Xj=20nm (taken at 5×1018at.∕cm3), abruptness of 3nm/decade, and Rs=326Ω/◻.

Drive Current Enhancement in Sub- 40-nm CMOS Devices by Higher Carrier Activation with Laser Spike Annealing

We thoroughly investigated the impact of higher carrier activation using laser spike annealing (LSA). In our experiments, the annealing time was set at and the peak annealing temperature was estimated at , which was higher than that of the spike-rapid thermal annealing (RTA) used in this study. We analyzed the source-drain parasitic resistance and the gate depletion suppression to demonstrate that LSA can improve currents while suppressing the short channel effect in sub- complementary metal oxide semiconductor devices, compared to the conventional spike-RTA. The gate depletion was suppressed by 0.18 and for p-MOS and n-MOS devices, respectively, and, channel conductance can actually be improved with it. Using LSA, a shallower junction depth and shorter source-drain extension (SDE) overlap length was achieved for the same SDE sheet resistance. As a result, the roll-off improved dramatically. Moreover, the higher carrier activation produced improvements in the current of 3%/14% for p-MOS/n-MOS transistors. We also demonstrate that a 13% improvement in was achieved for p-MOS at the same -roll-off as the spike-RTA device, due to the simultaneous suppression of gate depletion and the reduction in the source-drain parasitic resistance.

The Carbon Co-implant with Spike RTA Solution for Boron Extension

AbstractWe present B junction extensions that are extremely abrupt and shallow manufactured by amorphization, C co-implantation and conventional rapid thermal annealing (RTA). Resulting junctions have abruptnesses of 2 nm/dec better than as-implanted profiles. The most shallow B junction that has been manufactured is 15 nm deep and Rs = 626 Ω/sq. Successful implementation of these junctions is straightforward for P-MOS 30 nm gate length devices.

The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension

AbstractAs extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.