Drive Current Enhancement in Sub- 40-nm CMOS Devices by Higher Carrier Activation with Laser Spike Annealing

Abstract

We thoroughly investigated the impact of higher carrier activation using laser spike annealing (LSA). In our experiments, the annealing time was set at and the peak annealing temperature was estimated at , which was higher than that of the spike-rapid thermal annealing (RTA) used in this study. We analyzed the source-drain parasitic resistance and the gate depletion suppression to demonstrate that LSA can improve currents while suppressing the short channel effect in sub- complementary metal oxide semiconductor devices, compared to the conventional spike-RTA. The gate depletion was suppressed by 0.18 and for p-MOS and n-MOS devices, respectively, and, channel conductance can actually be improved with it. Using LSA, a shallower junction depth and shorter source-drain extension (SDE) overlap length was achieved for the same SDE sheet resistance. As a result, the roll-off improved dramatically. Moreover, the higher carrier activation produced improvements in the current of 3%/14% for p-MOS/n-MOS transistors. We also demonstrate that a 13% improvement in was achieved for p-MOS at the same -roll-off as the spike-RTA device, due to the simultaneous suppression of gate depletion and the reduction in the source-drain parasitic resistance.