Novel Laser Annealing Process for Advanced Complementary Metal Oxide Semiconductor Devices with Suppressed Polycrystalline Silicon Gate Depletion and Ultra shallow Junctions

Abstract

One of the major challenges in advanced complementary metal oxide semiconductor (CMOS) technology is to achieve an adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. We investigated gate pre annealing by laser thermal process (LTP) in conjunction with laser spike annealing (LSA) source/drain (S/D) activation to effectively suppress poly-Si gate depletion while forming highly activated ultra shallow junctions for S/D. We found that carrier concentration at the poly-Si gate/gate oxide interface increases and, accordingly, electrical inversion oxide thickness (Tinv) decreases whereas dopant penetration into the Si substrate is suppressed to a level far below that in conventional rapid thermal annealing (RTA). We realized improved device performance characteristics such as a high drive current, a small threshold voltage (Vth) shift, and a reduced off current (Ioff).