Speed-independent Circuits Research Articles

Detailed implementation of asynchronous circuits on commercial FPGAs

This paper provides the essential details of implementing 4-phase bundled data and speed independent asynchronous circuits on FPGAs. The required Xilinx synthesis tools including attributes, constraints and hardware implementation of basic asynchronous elements like Cgate, delay line, and handshaking modules are discussed. Finally, two design and implementation examples of asynchronous circuits are introduced. In order to reduce area and energy overhead, an N-stage pipeline with internal loops is proposed and employed in asynchronous Fuzzy Logic Controller (FLC). It is observed that synchronous FLC operating at 100 MHz consumes 27% more dynamic power while occupying 23% fewer FPGA resources compared to its asynchronous counterpart. At the same time, the asynchronous circuit has obtained an improvement of 19% in FLC performance compared to synchronous FLC. The other implementation example explains the technical details of the design and implementation process of speed independent circuit using Petrify and ISE at the LUT level. Both design examples are implemented and tested successfully on FPGA board.

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

Semi‐modular delay model revisited in context of relative timing

A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits is presented. While previous definitions ignore such constraints, the new definition takes them into account. The difference on a design solution for a well-known speed-independent circuit implementation of the Muller C element and a set of relative timing constraints that renders the implementation hazard free is illustrated. The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.

Signal transition graph decomposition: internal communication for speed independent circuit implementation

Logic synthesis of speed independent circuits based on signal transition graph (STG) decomposition is a promising approach to tackle complexity problems like state-space explosion. Unfortunately, decomposition can result in components that in isolation have irreducible complete state coding conflicts. In earlier work, the authors showed how to resolve such conflicts by introducing internal communication between components, but only for very restricted specification structures. Here, they improve their former work by presenting algorithms for identifying delay transitions and inserting gyroscopes for specifications having a much more general structure. Thus, the authors are now able to synthesise controllers from real-life specifications. For all algorithms, they present correctness proofs and show their successful application to benchmarks, including very complex STGs arising in the context of control resynthesis.

Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits

A fast and accurate simulator with elaborate hazard detection capabilities is vital for asynchronous circuits, not only for the purpose of design validation through logic simulation, but even more importantly for the purpose of test validation through fault simulation. Towards this end, we developed SPIN-SIM, a logic and fault simulator built around Eichelbergerpsilas classical hazard detection method, yet extended in various ways in order to overcome its limitations. More specifically, in order to improve simulation accuracy and hazard detection, SPIN-SIM i) employs a 13-valued algebra for which it adapts Eichelbergerpsilas method, ii) maintains partial orders of causal signal transitions through relative time-stamps, and iii) unfolds time-frames judiciously to distinguish between hazards and actual transitions. Experimental results demonstrate that, at the cost of a negligible increase in computational time over Eichelbergerpsilas method, if any at all, SPIN-SIM achieves significantly more accurate logic simulation and, by extension, drastically more efficient fault simulation. Furthermore, while the proposed method was developed and is presented for the class of speed-independent circuits, it is easily extendible to various other classes of asynchronous circuits.

A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks

In order to understand and analyse genetic regulatory networks (GRNs), the complex control structures which regulate cellular systems, well supported qualitative formal modelling techniques are required. In this paper, we make a case that biological systems can be qualitatively modelled by speed-independent circuits. We apply techniques from asynchronous circuit design, based on Signal Transition Graphs (STGs), to modelling, visualising and analysing GRNs. STGs are a Petri net based model that has been extensively used in asynchronous circuit design. We investigate how the sufficient conditions ensuring that an STG can be implemented by a speed-independent circuit can be interpreted in the context of GRNs. We observe that these properties provide important insights into a model and highlight areas which need to be refined. Thus, STGs provide a well supported formal framework for GRNs that allows realistic models to be incrementally developed and analysed. We demonstrate the proposed STG approach with a case study of constructing and analysing a speed-independent circuit specification for the lysis-lysogeny switch in phage λ.

Asynchronous system synthesis based on direct mapping using VHDL and Petri nets

A technique is proposed to synthesise system behavioural specifications written in VHDL into speed-independent asynchronous circuits constructed using David cells. This technique combines the advantages of logic synthesis and syntax-directed translation techniques. Coloured Petri nets and labelled Petri nets are used as intermediate formats for datapath and control representation. Speed-independent asynchronous circuits are obtained from these nets via direct translation. Several examples demonstrate the viability of the technique, which produces superior results compared with other ones.

Relative timing [asynchronous design

Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated.

STG-level decomposition and resynthesis of speed-independent circuits

This paper presents a time-efficient method for the decomposition and resynthesis of speed-independent (SI) circuits. Given the specification of an SI circuit, our method first generates its standard C implementation. Then, the combinational decomposition is performed to decompose each high-fanin gate that does not exist in the gate library into some available low-fanin gates. The time efficiency of our method is achieved in two ways. First, the signal transition graph (STG), whose complexity is polynomial in the worst case, is adopted as our input specification. Second, to reduce the resynthesis cycles, which constitute a major part of the run time, our method first investigates the hazard-free decomposition of each high-fanin gate without adding any signals. Then, for those gates that cannot be decomposed hazard free, two signal-adding methods constructed at the STG level are developed for resynthesis. This decomposition and resynthesis process is iterated until all high-fanin gates are successfully decomposed or no solution can be found. Several experiments on asynchronous benchmarks show that our method largely reduces run time with only a little more area expense when compared with previous work.

Decomposition and technology mapping of speed-independent circuits using Boolean relations

This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G available in the library and two gates H/sub 1/ and H/sub 2/ simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/ the method uses Boolean relations as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, the overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for sharing of decomposed logic. Overall, this method is more general than the existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping.

Logic decomposition of speed-independent circuits

Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates and (2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks.

The asynchronous counterflow pipeline bit-serial multiplier

Abstract We propose a novel architecture of an asynchronous bit-serial multiplier with counterflow data streams. The crucial idea of the proposed design is that data transfer between basic cells is acknowledged by another data transfer in the opposite direction. This design solution has resulted in lower hardware complexity because there is no extra acknowledged circuitry. For the multiplier design, a mixed-mode delay model is adopted. First, the control circuit of the multiplier's basic cell is designed as a speed-independent circuit. Then the method for interconnecting basic cells into a 1D array is presented. Finally, we incorporate data-path function into the basic cell under the bounded-delay model.

Covering conditions and algorithms for the synthesis of speed-independent circuits

This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean covering conditions that guarantee that the standard C-implementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable, but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal single-cube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our single-cube algorithm is applicable on most benchmark circuits and reduces run times by over an order of magnitude. The block-level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate-level speed-independent circuits.

Structural methods for the synthesis of speed-independent circuits

Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally expensive methods. This work presents new methods for the synthesis of speed-independent circuits from a new perspective, overcoming both the analysis and computation complexity bottlenecks. The circuits are specified by free-choice signal transition graphs (STGs), a subclass of interpreted Petri nets. The synthesis approach is divided into the following steps: correctness, binary coding, implementability conditions, and logic synthesis. Each step is efficiently implemented by applying a set of structural techniques that analyze STGs without explicitly enumerating the underlying state space. Experimental results show that circuits can be generated from specifications that exceed in several orders of magnitude the largest STGs ever synthesized-with over 10/sup 27/ states. Computation times are also dramatically reduced. Nevertheless, the quality of results does not suffer from the use of structural techniques.

Hazard-free implementation of speed-independent circuits

This paper develops a theoretical framework for the hazard-free gate-level implementation of speed-independent circuits specified by event-based models, such as signal transition graphs (for processes with AND causality and input choice) or their extension, called change diagrams (which allow OR-causality). It presents sufficient conditions, called the generalized monotonous cover requirements, for a hazard-free circuit to be built within a standard implementation structure. This structure consists of two-level simple-gate combinational logic and a row of latches, either a C-element or an RS-latch. A set of semantic-preserving transformations is defined that can be applied to an original behavioral description of the circuit so as to produce its specification in the form that satisfies the monotonous cover requirement. The transformations are applied at the event-based representation level (to avoid state explosion) and proved to be effective. The main result of the paper is therefore twofold: 1) the proof that any speed-independent behavior can be implemented at the gate level without hazards and 2) an efficient method for constructing such an implementation. Experimental results show that the proposed method compares very favorably, in area and performance, to the previously known techniques.

A region-based theory for state assignment in speed-independent circuits

State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples.

Estimation of energy consumption in speed-independent control circuits

We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per external signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high-level operation, and to provide average circuit power when combined with delay information.

Retargeting a hardware compiler using protocol converters

Abstract We show how to retarget a compiler for occam-like programs from generating two-phase delay-insensitive circuits to generating four-phase speed independent circuits. The specifications of the two-phase circuit elements for our compiler are used to produce a set of equivalent specifications for four-phase circuit elements using a set of protocol converters. Automatic tools have been used in checking that our four-phase implementations satisfy their specifications.

Verification of speed-independent data-path circuits

The paper demonstrates that verification techniques developed for relatively large, synchronous circuits can be applied to speed-independent, self-timed circuits. Local formulas are introduced which provide a natural way to specify the input/output behaviour of data-path circuits. The validity of a local formula is independent of the order in which the operations occur in a speed-independent circuit. The approach is demonstrated with the verification of a FIFO and a vector multiplier chip.

Communicating processes in designing asynchronous circuits

Asynchronous circuits are circuits that operate without a common global clock. They are potentially suitable for low-power devices. This paper describes an approach to verify speed-independent asynchronous circuits by using a protocol validation tool.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>