Abstract
A technique is proposed to synthesise system behavioural specifications written in VHDL into speed-independent asynchronous circuits constructed using David cells. This technique combines the advantages of logic synthesis and syntax-directed translation techniques. Coloured Petri nets and labelled Petri nets are used as intermediate formats for datapath and control representation. Speed-independent asynchronous circuits are obtained from these nets via direct translation. Several examples demonstrate the viability of the technique, which produces superior results compared with other ones.
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