Spatial Wavefunction Switched Research Articles

Simulation and Comparative Study of Propagation Delay in Multi-Channel Quantum SWS-CMOS-Based Inverters Using II–VI Gate Insulator

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Compute-in-Memory SRAM Cell Using Multistate Spatial Wavefunction Switched (SWS)-Quantum Dot Channel (QDC) FET

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

Design and Simulation of Multi-State D-Latch Circuit Using QDC-SWS FETs

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

Propagation Delay Evaluation for Spatial Wavefunction Switched (SWS) FET-Based Inverter

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

Power Dissipation and Cell Area: Quaternary Logic CMOS Inverter vs. Four-State SWS-FET Inverter

Power dissipation of spatial wave function switched (SWS) FETs four-state inverter is the focus of this paper. The current can flow through multiple channels in a (SWS)-FETs, which comprises vertically stacked quantum well/quantum dot channels. Using four voltage levels, the four-state SWS transistor inverter circuit is simulated. Cadence was used to perform SWS-FET inverter circuit simulations to evaluate power dissipation. To develop the SWS-FET model, an Analog Behavioral Model (ABM) and the Berkeley Short-Channel IGFET Model (BSIM4.6) were combined. To evaluate the inverter circuit’s transient behavior, a 0.18-μm technology node was used. The improvement in power dissipation, the frequency of operation, and reduction in cell area are all approximately is by a factor of 2-3. As a result, circuits based on SWS-FET inverters overcome the limitations of earlier implementations of 4-state logic circuits.

A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic

Multi-state room temperature operation of SiOx-cladded Si quantum dots (QD) and GeOx-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density nQM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).

3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

Multi-Bit SRAMs, Registers, and Logic Using Quantum Well Channel SWS-FETs for Low-Power, High-Speed Computing

This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.

Simulation of Stacked Quantum Dot Channels SWS-FET Using Multi-FET ABM Modeling

This paper presents simulation of spatial wavefunction switched (SWS) field-effect transistors (FETs) comprising of two vertically stacked quantum dot channels. An analog behavior model (ABM) was used to compare the experimental I-V characteristics of a fabricated QD-SWS-FET. Each channel consists of two quantum dot layers and are connected to the dedicated drains D2 and D1, respectively. The fabricated SWS-FET has one source and one gate. The ABM simulation models SWS-FET comprising of two independent conventional BSIM FETs with their (W/L) ratios, capacitances and other device parameters. The agreement in simulation and experimental data will advance modeling of SWS based adders, logic gates and SRAMs.

Integration of Quantum Dot Gate (QDG) in SWS-FETs for Multi-Bit Logic and QD-NVRAMs for Distributed In-Memory Computing

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Multi-State 2-Bit CMOS Logic Using n- and p- Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs

Unlike conventional FETs, spatial wavefunction switched (SWS)-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The aim of this paper is to present 4-states/2-bit output-input transfer characteristics using two Si/SiGe quantum well channels configured as CMOS using n- and p-channel spatial wavefunction switched field-effect transistors (SWS-FETs). Quantum simulations show switching of wavefunctions as the gate voltage is increased from lower Si quantum well to the upper well in n-channel and from upper SiGe quantum well to lower well in the p-channel. The inverter transfer characteristic and current switching are obtained by integrating BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). The simulation shows current flow only during switching.

Twin Drain Quantum Well/Quantum Dot Channel Spatial Wave-Function Switched (SWS) FETs for Multi-Valued Logic and Compact DRAMs

This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs

In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.