Multi-Bit SRAMs, Registers, and Logic Using Quantum Well Channel SWS-FETs for Low-Power, High-Speed Computing

Abstract

This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.