Spacer Etch Research Articles

Integration of Wet Cleaning in 45 Nm Pitch BEOL Processing

A partial-trench via first with self-aligned double patterning (SADP) approach is used to realize a 45 nm pitch using a dual damascene compatible hardmask. This back-end of line (BEOL) integration approach is used to investigate the ability to integrate advanced low-k materials and more specifically to assess their patterning performance. Throughout this SADP integration approach, different specific cleaning steps are required. A first cleaning process is needed after spacer etch and amorphous-carbon (a-C) strip to remove the spacer etch residues that are formed. Further in the integration flow, a TiN clean is needed together with a post-etch residue removal (PERR) after low-k etch.

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.

Novel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensions

A high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of 4.4 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> =1 V) are obtained.

Patterning Aspects of SiGe/Ge BFFT Fabrication

The sub20-nm wide SiGe bulk FinFET (BFFT) transistor structures have been fabricated by top-down direct patterning of the blanket strain-relaxed buffer (SRB) SiGe layer. The results of both the SiGe FIN patterning and the offset spacer etch stopping on a strained Ge channel are presented in this paper. The SiGe FIN geometry has been adapted starting from 300-nm deep (used for Si BFFT) to a 100-nm shallow but tapered FIN structure by using a newly-developed HBr/Cl2/O2/CH2F2 etch chemistry. Following standard replacement metal gate (RMG) flow, an offset spacer etch has been performed by using the low-bias CH3F/O2-based chemistry applied either with or without a SiCl4 additive. The best spacer-etch selectivity of 20 towards both the SiO2 and the Ge layers has been achieved at 200V bias and 75oC chuck temperature for the recipe selected. The final validation of the process has come from the following step of successful low-thermal-budget epitaxial growth of SiGe in the source-drain region (used for silicidation), which would not happen if there was complete consumption of the 20-nm thick strained Ge channel.

Pulsed-laser atom probe tomography of p-type field effect transistors on Si-on-insulator substrates

Forty-five nanometer gate length p-type field effect transistors fabricated on Si-on-insulator substrates were analyzed using three-dimensional pulsed laser atom probe tomography. An optimized sample preparation methodology involving spacer etching and a change in sample orientation to align the Si/buried-SiO2 interface with the analysis direction was developed to overcome the inherent difficulties in field evaporation of insulating materials present in the device structure. Atom probe tomography analysis of samples prepared in this cross-sectional orientation was used to observe B segregation to the gate SiO2 at 5 nm from the edge of the gate, from both the poly-Si gate doping as well as the source–drain extension ion-implantation following rapid thermal annealing at 900 °C for 16 or 32 s.

Wet Cleaning and Surface Preparation for Ge

In the process flow with Ge material, several wet cleaning steps are considered as post Ge channel deposition, post gate etch and post spacer etch. For these cleanings, not only high PRE (Particle Removal Efficiency) but also the control of Ge loss is required. We confirmed the characteristic of PRE on the Ge surface and Ge loss with conventional chemistries. Particles can be removed by the lift-off phenomena using ozonated water but a large amount (> 3nm) of Ge loss were required to obtain sufficient PRE. Applying diluted APM for high pH oxidation chemistry can minimize Ge loss while keeping effective particle removal. However since evaluated APM (1:1:20,000) still etches Ge layer first, it might have an issue of the concentration controllability and reproducibility. In this paper, we demonstrated a novel chemistry alternative to highly diluted APM that has proven significant competitive advantages.

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

A comprehensive model predicting the effects of plasma-induced damage (PID) on parameter variations in advanced metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. The model focuses on the silicon recess structure (Si loss) in the source/drain extension region formed by high-energy ion bombardment during plasma etching. The model includes the following mechanisms: (1) damaged layer formation by ion impact and penetration, (2) Si recess structure formation by a subsequent wet etch, (3) MOSFET performance degradation, and (4) MOSFET parameter variation. Based on a range theory for plasma-etch damage, the thickness of the damaged layer exhibits a power-law dependence on the energy of the ion incident on the surface of Si substrate. Assuming that the damaged layer was formed during a gate or an offset spacer etch process, the depth of Si recess (dR) is a function of the depth profile of the created defect site (ndam), the wet-etch stripping time (tw), and the energy of the incident ion. It was found that dR also showed a power-law dependence on the average ion energy E−ion estimated from applied self-dc-bias voltage for various tw. As for MOSFET performance degradation, the threshold voltage (Vth) shifted and the shift (ΔVth) increased with an increase in E−ion and a decrease in gate length. This induces an increase in subthreshold leakage current (Ioff) for MOSFET. Technology computer-aided-design simulations were performed to confirm these results. By integrating the presented PID models, parameter variations could be predicted: Using a Monte Carlo method, it was demonstrated that PID increases parameter variations such as Vth and Ioff. It also was found that the variation in E−ion induces Vth and Ioff variations, comparable to that induced by other process parameter fluctuations such as dopant fluctuation and gate length. In summary, considering the effects of PID on parameter variations is vital for designing future ultralarge-scale-integrated circuits with billions of built-in MOSFETs.

Ultrahigh selective etching of Si3N4 films over SiO2 films for silicon nitride gate spacer etching

The process window for the high etching selectivity of silicon nitride to silicon oxide was investigated in CF4∕CH4 inductively coupled plasma. This work showed that the etching selectivity could be controlled by modulating the thickness of the fluorocarbon film with the flow rates of CH4 gas. The carbon content in the fluorocarbon by-product layers on the etched films was observed to play a critical role in determining the etching selectivity of silicon nitride to silicon oxide. The increase in the carbon content in the fluorocarbon films with increasing CH4 gas caused the etch rates of both silicon oxide and silicon nitride films to be reduced, eventually leading to the etch stops. The minimum effective thickness of the fluorocarbon films was estimated to be 20Å for the etch stop. The infinite etching selectivity of the silicon nitride to the silicon oxide on the blanket wafers could be achieved for the CH4 flow rate above 30SCCM (SCCM denotes cubic centimeters per minute at STP) for the CF4 flow rate of 10SCCM. NF3∕CH4 and SF6∕CH4 plasma showed etch behavior similar to CF4∕CH4 plasma.

Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at &amp;lt;200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage &amp;gt;8 MVcm−1 and leakage current &amp;lt;1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.

Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess (dR) was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift (DeltaVth) and d R was found. Device simulations were also performed for n-MOSFETs with various (dR). Both |DeltaVth| and off-state leakage current increased with an increase in d R . The increase in |DeltaVth| becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances Vth-variability in future devices.

Yield Enhancement with Optimized Offset Spacer Etch for 65nm Logic Low-leakage Process

This paper presents an effective way to reduce the degradation of the Ring-OSC speed with optimized offset spacer etch, improvement of the within-wafer uniformity of the offset spacer width and the reduction of its profile deviation. We have developed the lower offset spacer etch rate scheme for better control of plasma uniformity in order to achieve the above two targets. Compared with the 3Sigma of 1.3nm offset spacer width uniformity and 1.8nm profile deviation of conventional dielectric etcher with high etch rate, this low etch rate process has delivered the 3sigma of 0.5nm for the offset spacer width uniformity and 0.7nm offset spacer profile deviation. The corresponding Ring-OSC loss has been completely eliminated and the wafer-level yield is enhanced by 40%.

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single- gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.

Study of plasma charging-induced white pixel defect increase in CMOS active pixel sensor

Plasma process-induced “white pixel defect” (WPD) of CMOS active pixel sensor (APS) is studied for Si3N4 spacer etch back process by using a magnetically enhanced reactive ion etching (MERIE) system. WPD preferably takes place at the wafer edge region when the magnetized plasma is applied to Si3N4 etch. Plasma charging analysis reveals that the plasma charge-up characteristic is well matching the edge-intensive WPD generation, rather than the UV radiation. Plasma charging on APS transfer gate might lead to a gate leakage, which could play a role in generation of signal noise or WPD. In this article the WPD generation mechanism will be discussed from plasma charging point of view.

Nanoflash device with self-aligned double floating gates using scanning probe lithography and tetramethylammonium hydroxide wet etching

We report a self-aligned technology for nanoflash devices with double floating gates using scanning probe lithography (SPL) technology and anisotropic wet etching. On a (110) SOI silicon wafer, along [001] and [111] directions, a silicon nanowire was generated through local oxidation with SPL followed by wet etching with tetramethylammonium hydroxide solution. Silicon nanowires (SiNW) with profiles of sidewall either sloped or vertical were formed after anisotropic etching in the [001] or [111] direction respectively. After deposition of a polysilicon film on the SiNW with low pressure chemical vapor deposition, nanostructures of a nanoflash device with polysilicon double-floating side gates were obtained along the [111] part of SiNW after reactive ion etching spacer etching. The silicon nanowire channel has a width of 20 nm and a height of 200 nm; the width of the self-aligned floating gate is approximately 40 nm. Silicon nitride was deposited to serve as gate dielectric. The top gate and source-drain aluminum pads were defined by photolithography. Electrical properties of such a nanoflash device with double-floating side gates are discussed.

Development of a Post-Spacer Etch Clean to Improve Silicide Formation

ABSTRACTThe formation of a uniform, low-resistance silicide is dependent on the contamination level of the silicon surface upon which the Ti or Co is deposited. Contamination may be in the form of embedded carbon and fluorine residues from previous processing steps, such as the LDD spacer etch. The extent to which the spacer etch contributes impurities can be determined by making contact angle measurements; that is, measurement of the angle formed by a droplet of water placed on the wafer surface. A clean silicon surface provides a contact angle of &gt; 70°, whereas a contaminated silicon surface produces contact angles down to only a few degrees. By using contact angle as a metric, a post-spacer etch clean was developed to remove impurities from the silicon surface without significant silicon loss. The clean procedure entails the use of a CF4/H2O plasma to treat the wafer directly after spacer etch. The clean process was then evaluated by the formation of a blanket Ti silicide followed by sheet resistance measurement. By using this cleaning process, a Ti silicide sheet resistance comparable to that formed on virgin silicon wafers was obtained on wafers that experienced the spacer etch. By comparison, wafers that were subjected to the spacer etch but not the post-spacer clean yielded a higher sheet resistance. Additional study of the post-spacer etch clean process revealed that oxide on the wafer (even the small amount formed during an O2-based resist ash process) can prevent the CF4/H2O plasma from cleaning the surface, perhaps by blocking H in the cleaning plasma from extracting C and other contaminants from the silicon surface. Co silicide formation is even more sensitive to surface impurities than Ti silicide. Using the same post-spacer etch clean, uniform, low-resistance Co silicide formation has been demonstrated.

The leakage current improvement in an ultrashallow junction NMOS with Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 /spl Aring/ have been studied. In order to minimize the junction leakage current, the thickness of the CoSi/sub 2/ layer should he controlled under 300 /spl Aring/ and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi/sub 2/ layer into the channel direction when the gate spacer length was larger than 400 /spl Aring/.

Process characterisation of hot-carrier-induced β degradation in bipolar transistors for BiCMOS

This paper investigates the effect of various process parameters on the variation in forward current gain lifetime caused by hot carrier generation of BiCMOS bipolar transistors. Statistical process control and statistical designed experiments were used in this evaluation. The device lifetime in reverse bias operation was calculated from the forward current gain. Various process parameters were examined in this work, i.e., the intrinsic base implant dose and energy, selective collector implant dose, collector plug dose, spacer etch ratio, overetch thickness of nitride spacer and emitter poly etch time. It was deduced that high current gain lifetime can be obtained with high base implant doses, high base implant energies, long bulk nitride etch times and short emitter poly etch times.

Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule

Double Spacer local oxidation of silicon (LOCOS) with shallow recess of silicon (DS-LOCOS) is described. The process has two spacers, a thin nitride spacer and a medium temperature chemical vapor deposition (CVD) oxide spacer. The process does not have intentional silicon recess etching step but achieves the shallow recess of silicon through nitride overetchings. It has been found that the key processes of the DS-LOCOS are both isolation etching and spacer etching, which critically affect 2ΔW and V t roll-off behaviors of active transistor and junction characteristics. The DS-LOCOS achieves physical bird's beak length of below 0.03 µ m/side, field oxide volume ratio over 80%, and superior planar surface. The DS-LOCOS also gives no degradation in punchthrough voltage down to 0.20 µ m isolation spacing and in gate oxide reliability. These results show that the DS-LOCOS is a simple and promising isolation technology for sub-quarter micron design rule.

Monitoring of Sidewall Spacer Etch by Optical Emission Spectroscopy and Mass Spectroscopy

ABSTRACTSelective etch of SiO2/poly Si in a high density CF4+D2 plasma generated by ECR (Electron Cyclotron Resonance) system was studied. The end point detection of the SiO2 sidewall spacer etch was monitored using optical emission spectroscopy and mass spectrometer. SEM cross sectional analysis was conducted to confirm the end point detection and spacer formation.

Examination of fluorocarbon-based plasmas used in the selective and uniform etching of silicon dioxide by response-surface methodology: Effects of helium addition

The process parameter space for fluorocarbon plasmas (C2F6/CHF3 and CF4/CHF3, with and without He) which are used to etch SiO2 has been examined with a Lam Research Autoetch 580 parallel plate, single‐wafer etching system by response‐surface methodology. The response or behavior of the plasmas differs very significantly with reactor pressure, etch gas mixture, and He addition. In particular, substantially higher SiO2 etch rates are obtained with C2F6/CHF3 plasmas than with CF4/CHF3 plasmas at an equivalent radio frequency power density for similar gas flow rates at significantly different reactor pressures: ∼2500 Å/min at ∼400 mTorr with C2F6/CHF3 mixtures and ∼750 Å/min at ∼1500 mTorr with CF4/CHF3 mixtures. Upon addition of He to the plasmas, the SiO2 etch rate maximum for the C2F6‐based plasma shifts to ∼800 mTorr and declines to ∼2000 Å/min, while that for the CF4‐based plasma remains near 1400 mTorr and increases to ∼1000 Å/min. Whereas the addition of He sharply degrades the etching uniformity with C2F6/CHF3 mixtures, it has no apparent effect on the etching uniformity with CF4/CHF3 mixtures, which is high with or without the addition of He over the parameter space which was explored. For the C2F6/CHF3 plasma, the etch selectivity to silicon is highest at 700–1100 mTorr, while for the CF4/CHF3 plasma the selectivity is highest at 1100–1500 mTorr. Although addition of He substantially improves the selectivity with the CF4/CHF3 plasmas, it has no effect on selectivity with the C2F6/CHF3 plasma. These detailed characterizations of process parameter space have led to a uniform and selective SiO2 sidewall spacer etching process which may be readily extended to other SiO2 etching processes with this equipment and these gas mixtures.