Patterning Aspects of SiGe/Ge BFFT Fabrication

Abstract

The sub20-nm wide SiGe bulk FinFET (BFFT) transistor structures have been fabricated by top-down direct patterning of the blanket strain-relaxed buffer (SRB) SiGe layer. The results of both the SiGe FIN patterning and the offset spacer etch stopping on a strained Ge channel are presented in this paper. The SiGe FIN geometry has been adapted starting from 300-nm deep (used for Si BFFT) to a 100-nm shallow but tapered FIN structure by using a newly-developed HBr/Cl2/O2/CH2F2 etch chemistry. Following standard replacement metal gate (RMG) flow, an offset spacer etch has been performed by using the low-bias CH3F/O2-based chemistry applied either with or without a SiCl4 additive. The best spacer-etch selectivity of 20 towards both the SiO2 and the Ge layers has been achieved at 200V bias and 75oC chuck temperature for the recipe selected. The final validation of the process has come from the following step of successful low-thermal-budget epitaxial growth of SiGe in the source-drain region (used for silicidation), which would not happen if there was complete consumption of the 20-nm thick strained Ge channel.