Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs

Abstract

As CMOS technology is downscaled into 22nm a transition from 2D to 3D transistors occurred and a revolutionary FinFET design was introduced. During this R&D, different strain engineering methods including selectively grown SiGe on source/drain as stressor material was used to boost the channel mobility. Another way to deal with channel mobility issue is to integrate Ge material which has high mobility for both p and n channel instead having Si fin in the transistor structure. In this study, the Si Fin is processed and subsequently removed to create the trench between the STI SiO2 and a SiGe/Ge bilayer is selectively grown to fill the trench that is used as the MOS channel. In principle, there are two methods to remove the Si Fins as shown Fig.1 Primarily using WET etch while the second method is using the HCl etch during the epitaxy process. Since SiGe/Ge epitaxy process is sensitive to surface quality of the Si Fin, a meticulous in-situ cleaning is essential to remove all undesired residuals from the Si surface.At first, selective Ge growth was applied to fill out the Si removed areas. The Ge layer is difficult to fill the small trenches (Fig.2a), therefore a SiGe layer is deposited as the strain relaxed buffer (SRB) layer in the trench prior to the Ge layer (Fig.2b). A Chemical Mechanical Polish (CMP) is necessary to planarize the surface (Fig.2c).The Ge content and the strain amount in the SiGe layers was directly measured using high-resolution x-ray diffraction (HRXRD) rocking curves (RC). RCs were done at (113) reflection where the incident beam is as low as 2.6° and a large area of sample containing an enormous of number of transistors could be covered by x-ray beam. These RCs were simulated by the Takagi-Taupin equations and compared to the experimental curves in order to obtain high precision data for analysis. Cross-section images where provided by high-resolution scanning electron microscopy (HRSEM) and transmission electron microscopy (HRTEM) to measure the layer thickness, epi-quality, and integrity of the whole transistor structures. In the latter analysis, energy dispersive spectroscopy (EDS) technique was also employed to reconfirm the Ge profile in the channel regions of the FinFETs. Reference s [1] Wang G, Abedin A, Moeen M, et al. Integration of highly-strained SiGe materials in 14nm and beyond nodes FinFET technology[J]. Solid-State Electronics, 2015, 103: 222-228. Figure 1