Abstract

Forty-five nanometer gate length p-type field effect transistors fabricated on Si-on-insulator substrates were analyzed using three-dimensional pulsed laser atom probe tomography. An optimized sample preparation methodology involving spacer etching and a change in sample orientation to align the Si/buried-SiO2 interface with the analysis direction was developed to overcome the inherent difficulties in field evaporation of insulating materials present in the device structure. Atom probe tomography analysis of samples prepared in this cross-sectional orientation was used to observe B segregation to the gate SiO2 at 5 nm from the edge of the gate, from both the poly-Si gate doping as well as the source–drain extension ion-implantation following rapid thermal annealing at 900 °C for 16 or 32 s.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.