Source Terminals Research Articles

Design of Hafnium Oxide (HfO<sub>2</sub>) Sidewall in InGaAs/InP for High-Speed Electronic Devices

The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO2 which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

Measurement of the Common Source Inductance of power devices with kelvin source terminal

Measurement of the Common Source Inductance of power devices with kelvin source terminal

Pseudo-Symmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications

The enclosed layout transistor is an alternative to reduce the radiation sensitivity of CMOS devices by avoiding thick field oxide paths between source and drain terminals. This prevents the increase of leakage current of devices working under radiation. The commonly adopted square geometry of this design brings asymmetry between source and drain, modifying characteristics such as output conductance and capacitance, if compared to a traditional layout. Therefore, considering analog designs, this may complicate the process of mapping a non-hardened design onto a radiation tolerant version, even if the aspect ratios ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$W/L$</tex-math></inline-formula> ) of the transistors are designed to be the same. In this paper, we propose a pseudo-symmetric version of enclosed layout devices in order to better approximate its electrical characteristics to the conventional layout style. This way, no significant modification on simulation and design validation flow is necessary. The devices were fabricated in a 130 nm process, being then characterized and compared with regular (non-symmetric) ELTs as well as to conventional (two-edge) layout transistors. Results show a good agreement between the tested parameters of the pseudo-symmetric ELTs and the correspondent two-edge devices.

Reflection Resource Management for Intelligent Reflecting Surface Aided Wireless Networks

In this paper, the adoption of an intelligent reflecting surface (IRS) for multiple user pairs in two-hop networks is investigated. Different from the existing studies on IRS that mainly focused on tuning the reflection coefficients of all elements, we consider the implementation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">true</i> reflection resource management (RRM) through the identification of the best triggered module subset. More precisely, the implementation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">true</i> RRM builds on the premise of our proposed modular IRS structure consisting of multiple independent and controllable modules. In the context of modular IRS structure, we investigate the signal-to-interference-plus-noise ratio (SINR)-based max-min problem subject to per source terminals (STs) power budgets and module size constraint, via joint triggered module subset identification, transmit power allocation, and the corresponding passive beamforming. Whereas this problem is NP-hard due to the module size constraint, which can be addressed by the convex sparsity-inducing approximation to the hard module size constraint using mixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ell _{1,F}\text {-norm}$ </tex-math></inline-formula> , where it yields a suitable semidefinite relaxation. Using techniques from separable convex programming, we provide a two-block alternating direction method of multipliers (ADMM) algorithm for the approximated problem. Numerical simulations are used to validate the analysis and assess the performance of the proposed algorithm as a function of the system parameters. Further energy efficiency (EE) performance comparison demonstrates the necessity and meaningfulness of the introduced modular IRS structure. Specifically, for a given network setting, there is an optimal value of the number of triggered modules for system, when the EE is considered.

Feedback Stabilization of a Negative-Capacitance Ferroelectric and its Application to Improve the f T of a MOSFET

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}$ </tex-math></inline-formula> compared to a conventional MOSFET.

FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm

The recent technologies in VLSI chips has grown in terms of scaling of transistor and device parameters but still there is a challenging task for controlling of current between source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip manufacturing, through which current can be effectively controlled. This section addresses the issues present in CMOS technology and majorly concentrated on proposed 4-bit Nano processor using FinFET 32nm technology by using Cadence Virtuoso software tool. In the proposed Nanoprocessor design, the first portion of the design is done using 4bit ALU which includes all basic and universal gates, high speed adder, multiplier and multiplexer. The Carry Save Adder (CSA) and multiplier are the major sub component which can optimize the power consumption and area reduction. The second portion of the proposed Nano processor design is 4-bit 6T SRAM and encoder and decoder and also using Artificial Neural Network (ANN). All these sub components are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS and at the last chip level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET using technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% with optimization in power dissipation of 47% along with optimization in leakage current, with 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses are compressed subsequently respectively. The basic gates, universal gates, CSA, subtraction and MUX are integrated for 4-bit ALU design and its delay, power consumption and area are found to be 0.104nsec, 314.4uW and 56.8μsqm respectively.

Development of compact inductive energy storage pulsed-power generator driven by 13 kV SiC-MOSFET.

A compact inductive energy storage (IES) pulsed-power generator that is driven by a novel 13 kV silicon carbide (SiC)-MOSFET is developed and molded into a compact modified TO-268. In this article, the switching characteristics required for IES pulsed-power generator development are evaluated. The maximum slew rates at MOSFET turn-on and turn-off are 157 and 129 kV/μs, respectively, at an input voltage of 10 kV. The maximum current flow from the drain to the source terminal is limited to 128A during short-circuit switching. The on-resistance between the drain and source terminals increases during the SiC-MOSFET's on state. It increases with the voltage and its minimum value is 1.07 Ω. These characteristics show that the device is suitable for use as an opening switch because of its low on-resistance and rapid large-current cutoff at high operating voltages. The characteristics of an IES pulsed-power generator composed of a SiC-MOSFET, a capacitor, and a pulsed transformer with a turn ratio of 5:15 are also evaluated. The output voltage peak and full width at half maximum reach 31.4 kV and 55ns, respectively, at a charging voltage of 1100V. The maximum energy transfer efficiency is 50.2% of the input energy with a load resistance of 2.5 kΩ. The results show that the MOSFET has excellent potential to support the development of a compact plasma generation system that offers better performance pulsed-power generators driven by semiconductor devices.

5‐2: Enhanced Bending Endurance with Transverse Tensile Strain and 4‐Terminal Double Gate LTPS TFTs for flexible AMOLED

This letter investigates the degradation behavior of p‐channel LTPS TFTs on PI substrate under the static bending stress. During 1hr bend, the threshold voltage shifts positively and the subthreshold slope increases slightly. In transverse compressive strain, the field effect mobility increases abruptly with the decrease of the effective channel length and the off state leakage current. This is attributed to the generation of the strain‐induced GI defects near the source and drain terminals, resulting in the trapping of electrons and a shrinkage of the effective channel length and the H passivation of the strained Si bonds in the channel. By inserting the bottom metal layer to block the H diffusion from PI substrate, the controllable normal NBTI behavior is observed in a strained LTPS TFT on PI. These transverse tensile strained and 4‐termianl double gate LTPS TFTs on PI shows as a stable switching TFTs on PI for the flexible system‐on‐panel display.

Operational Transconductance Amplifier-Based Electronically Controllable Memcapacitor and Meminductor Emulators

In this paper, two simple circuits are presented to emulate both memcapacitor and meminductor circuit elements. The emulation of these components has crucial importance since obtaining these high-order elements from markets is difficult when compared to resistor, capacitor and inductor. For this reason, we proposed Multi-Output Operational Transconductance Amplifier (MO-OTA)-based electronically controllable memcapacitor and meminductor circuits. To operate the MOS transistor as a capacitor, drain and source terminals are connected to each other. The memcapacitor behavior is obtained by driving the connected terminals with suitable voltage values. Only a few active and grounded passive components which are found in markets easily are used to emulate meminductive behavior. Furthermore, all passive elements in the circuit are grounded. All simulation results for memcapacitor and meminductor emulators are obtained successfully when compared to previous studies. For all analyses, MO-OTA is laid using the Cadence Spectre Analog Environment with TSMC 0.18[Formula: see text][Formula: see text]m process parameters and occupied a layout area of only 86.21[Formula: see text][Formula: see text]m.

High Transconductance Gain Current Differencing Transconductance Amplifiers Using a New Approach of gm Boosting

Two new structures of current differencing transconductance amplifier (CDTA) for high transconductance gains are proposed. Usually, the transconductance gain of conventional CDTA is controlled by varying the bias current which limits the transconductance gain up to a certain extent and increases the power dissipation. These problems have been eliminated by introducing a technique in which common source amplifiers are connected between gate and source terminals of the differential pair metal oxide semiconductor field effect transistors (MOSFETs) of conventional CDTA. The common source amplifiers are used to increase the gate-to-source voltages of differential pair MOSFETs which increase the transconductance gain of the proposed CDTA-I. To further increase the transconductance gain of the proposed CDTA-I, another structure namely, CDTA-II is also proposed which uses an ‘N’ number of n-type MOSFETs connected in parallel instead of a single n-type MOSFET in each side of the differential pair. The gate-to-source voltages of all ‘N’ parallel MOSFETs remain the same as in the proposed CDTA-I and the total output current of operational transconductance amplifier is increased and therefore, transconductance gain is further increased. The proposed CDTA-I and CDTA-II have been designed using Mentor Graphics Eldo tool. The simulation results have been obtained using 0.18 µm complementary metal oxide semiconductor technology parameters. The simulation results demonstrate that the transconductance gains of proposed structures have been increased significantly while power dissipations are the same as that of the conventional CDTA. The high-frequency Kerwin–Huelsman–Newcomb filters using both the proposed structures have also been presented to show the effectiveness of the proposed CDTAs.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design

This brief presents the design and sizing of a femto-watt voltage reference based on the temperature compensation of N-type and P-type standard transistors. A short-channel dimension transistor working in triode region is added between the source and gate terminals of the traditional self-bias structure, which demonstrates efficient low-power and low-voltage operations. The circuit design was carried out in a 180 nm process. Post-layout simulation results verified the proper circuit operation and produced a reference voltage of 65.7 mV. With a minimum supply voltage of 120 mV, the circuit consumes 252 fW at room temperature, has mean and best temperature coefficients (TCs) of 89.81 ppm/°C and 10.61 ppm/°C, respectively, from -40 to 120°C, and presents a power supply rejection ratio (PSRR) of -61 dB.

Analysis of single electron transistor using switched capacitor filter

This paper deals with electrical characteristic of Single-Electron Transistor (SET). The Current- voltage (I-V) characteristic of the SET is predicted according to various capacitance parameters. The Process of simulation is based on analytical transistor model. The effect of tunnelling capacitance on the I-V characteristics of SET are systematically computed assuming source and drain are connected by quantum dot. The Steady state equation is solved by considering the tunnelling mechanism. We calculated free energy changes as a function of equivalent circuit parameters and background charge. Tunnelling probabilities on drain and source terminals are determined using Fermi’s Golden Rule. The SET is the simplest device wherein coulomb blockade effect can be observed.

Compact Modeling of High-Voltage Gallium Nitride Power Semiconductor Devices for Advanced Power Electronics Design

This work presents a physics-based compact GaN device model that can predict the performance characteristics of a wide range of GaN devices for power electronics applications. The model has been validated against the measured characteristics of a 650 V commercially available GaN device. The higher voltage range devices exhibit quasi-saturation on-state behavior due to drift resistance, which is evident from their on-state behavior. Also, higher voltage GaN devices have significant nonlinear capacitance characteristics due to the presence of field plates connected to the source and gate terminals. The field plates are fabricated to improve the electric-field distribution in the channel. The field plates result in significant nonlinearity in the channel capacitance that can be quantified as successive depletion in the device capacitances. The model accurately captures these phenomena in the dc and C-V device characteristics. The model also captures the third-quadrant behavior of all GaN devices with model parameters that are decoupled from the first quadrant while maintaining continuity between the first and third quadrants. Dynamic validation of the model is performed from the double-pulse test. The proposed model can be used to characterize commercially available high-voltage GaN devices that can be used in power electronic applications and design.

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

In this report, we study nonlinear electrical behaviors found in vertical-architecture transistors based on wrap-around-gated gallium nitride (GaN) nanowires (NWs) by extending a one-dimensional case of the Landauer-Buttiker formula. Here, the GaN NWs are considered “almost” one-dimensional ideal wires connecting the drain and source terminals, with the gate terminal serving to control the flowing current. Unlike previous models, which require several parameters and complex calculations, our proposed model only needs three parameters and simple calculations to match the experimental data. With this model, we confirm that the maximum current before saturation is a consequence of quasi-ballistic drain current. Thus, electron mobility has no effect in this device. Using a simple formulation, we discuss gating hysteresis in the device that is mediated by the selected oxide layer interface. We show that the memory effect of the device is attributed to time-delay current. The shorter gate length increases the transmission coefficient. As a result, the model can be employed to predict the next-generation NW transistor performance.

Simulink implementation of three-phase PWM rectifier using five-level cascaded H-bridge MLI configuration

Ability of multilevel inverters (MLI) to operate with matured medium power electronic devices has enhanced their prominence for active front converters in various applications such as drive control, battery energy storage systems and PV/Grid integrated systems. In short, Active front end (AFE) converters are regenerative rectifiers incorporated to, simultaneously regulate dc-link voltage and ensure unity power factor at source terminals. Realizing the significance of MLI based active front end converter, this paper presents Simulink implementation of MLI based active front end converter, using most popular classical MLI i.e., cascaded H-bridge. Imposing level shifted and phase shifted carrier arrangements, implementation PWM for CHB is demonstrated and MATLAB simulation results for both open loop and closed systems are presented.

Room temperature terahertz detector based on single silicon nanowire junctionless transistor with high detectivity

In this work, the n-type single silicon nanowire (NW) based junctionless field-effect transistor (FET) is demonstrated as an efficient terahertz (THz) detector. For the effective coupling of the THz radiations with NW junctionless FET, the lobes of the rounded bow-tie antenna are connected to the gate and source terminals of the device. The antenna design is optimized with proper impedance matching conditions to achieve maximum power transfer between antenna and detector. The simulated antenna resonates at 0.43 THz frequency with 19 GHz bandwidth. Further simulations have been done on Lumerical finite difference time domain software to analyze the electric field distribution profile. To investigate the optical response of this optimized antenna design, an array of the simulated antenna has been fabricated and its transmission spectra are measured. Finally, the simulated antenna has been integrated with the n-type NW junctionless transistor. A maximum responsivity of 468 V W−1 at 0.425 THz frequency and noise-equivalent-power of ∼ 10−9W/Hz1/2 is obtained at room temperature. The complementary metal-oxide-semiconductor’s compatibility, ease of integration on chips, possibility to realize multiple pixel arrays, andscalability to higher frequencies, make this device promising for THz electronics.

STUDY ELECTROMAGNETIC WAVE INTERACTION OF ACTIVE-MATRIX THIN FILM TRANSISTORS

Active-matrix thin film transistors (TFTs) on glass substrates with a metal backplane, that are applied for flat panel displays, can be considered as a metamaterial absorber. In this study, TFT structures using doped silicon at source, drain, and channel terminals are investigated. These terminals are unchanged in size of 75 µm square and thickness of 5.3 µm. The electric conductivity is varied at the channel. The simulation results show that the structures with 500 S\m electric conductivity channels absorb incident electromagnetic waves with appropriately 100% at 758 GHz and a wide bandwidth of 20 GHz. As the electrical conductivity increases, the absorption and bandwidth are smaller at the main resonance peak. As the electrical conductivity decreases, the absorption falls at the resonance frequency, but the bandwidth is broadened. In addition, the electric field in the channel may influence the electron in the semiconductor and the electrical current between the source and drain terminals. By observing the electric field at the resonance frequency, we found that it is focused on the sides of channel terminals.

Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers

An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.

C‐MRC–based cooperative spatial modulation with antenna selection

SummaryA new high‐performance low‐complexity cooperative maximal ratio combining (C‐MRC)‐based cooperative relaying scheme, which is called antenna selection‐aided cooperative spatial modulation scheme with C‐MRC (AS‐CSM), is proposed for decode and forward (DF)‐based cooperative relaying networks operating over independent but non‐identically distributed (i.n.d.) Rayleigh fading channels. The AS‐CSM scheme is formed with the combination of cooperative SM with the high‐performance low‐complexity coherent demodulator C‐MRC and antenna selection techniques. In the AS‐CSM scheme, the information is transmitted from the source terminal (ST) to the relay terminal (RT) and the destination terminal (DT) in the form of not only modulated symbols but also antenna indices, which carry additional information bits in the spatial domain. Therefore, a high spectral efficiency is obtained by the proposed scheme for cooperative relaying networks. In this scheme, first, the index of the activated antenna of ST is estimated, and the best antenna selection at RT is investigated considering the received instantaneous equivalent to signal‐to‐noise values acquired at DT. The transmitted symbols are estimated with low‐complexity coherent demodulator C‐MRC at DT by using the noisy signals from ST and RT. An exact closed‐form expression for the bit error probability (BEP) of the AS‐CSM scheme is derived, and the theoretical results are validated with Monte‐Carlo simulation results.