Pseudo-Symmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications

Abstract

The enclosed layout transistor is an alternative to reduce the radiation sensitivity of CMOS devices by avoiding thick field oxide paths between source and drain terminals. This prevents the increase of leakage current of devices working under radiation. The commonly adopted square geometry of this design brings asymmetry between source and drain, modifying characteristics such as output conductance and capacitance, if compared to a traditional layout. Therefore, considering analog designs, this may complicate the process of mapping a non-hardened design onto a radiation tolerant version, even if the aspect ratios ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$W/L$</tex-math></inline-formula> ) of the transistors are designed to be the same. In this paper, we propose a pseudo-symmetric version of enclosed layout devices in order to better approximate its electrical characteristics to the conventional layout style. This way, no significant modification on simulation and design validation flow is necessary. The devices were fabricated in a 130 nm process, being then characterized and compared with regular (non-symmetric) ELTs as well as to conventional (two-edge) layout transistors. Results show a good agreement between the tested parameters of the pseudo-symmetric ELTs and the correspondent two-edge devices.