Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology

Abstract

Enclosed Layout Transistors (ELT) comprise a feasible design alternative to hardening CMOS circuits against total ionizing dose effects. This design technique significantly reduces the leakage paths produced by trapped charges in the field oxide of regular NMOS devices. This work presents the characterization of several ELT devices designed and fabricated on a 130nm technology aiming at analog applications. Standard (rectangular) transistors with equivalent aspect ratio were also considered for comparison. The experimental data are compared with simulations performed using a commercial design tool, considering the aspect ratio (W/L) extracted from the layout. ELTs with the drain designed both as the inner and outer terminal were characterized and compared. Additionally, in order to improve the achievable aspect ratio range of the square ELTs, parallel and series associations of enclosed devices were implemented as well. According to obtained results, there may be significant differences between the W/L extracted from the design tool and its actual value in the fabricated device. For all enclosed devices, the simulation overestimates the current values. A different pattern regarding the influence of drain location (inner or outer terminal) on current performance is also observed when comparing measured data with simulations. Additionally, associations of ELT showed to be feasible to widen the range of possible aspect ratio of this particular transistor.