Performance and simulation accuracy evaluation of analog circuits with enclosed layout transistors

Abstract

This paper presents an investigation on two important issues related to the application of enclosed layout transistor (ELT) to the design of analog building blocks: the performance impacts, related to the geometrical asymmetry and capacitances of drain and source terminals and the possible errors of commercial design tools when performing the layout versus schematic and layout extraction tasks. A common-source (CS) amplifier is considered as case study, to which the ELT layout technique is applied. SPICE simulations are performed, considering different methodologies to estimate the effective aspect ratio (W/L) of the ELT devices. The extracted equivalent W/L using a commercial design tool is compared with well-known mathematical models presented in the literature. Simulations were carried out considering three different channel lengths for the CS amplifier. The possibility of setting the transistor drain as inner or outer terminal of the ELT was also investigated. According to obtained results, considering a 0.18 µm technology, there may be significant performance differences, both in DC and AC behavior of the amplifier, and significant divergences of the extracted W/L, when compared to the analyzed models. Additionally, in order to improve the achievable aspect ratio range of square ELTs, we propose to use parallel and series associations of enclosed devices. Depending on the desired W/L, it is also possible to save silicon area with such associations.