The scaling of silicon CMOS faces several obstacles necessitating the need to introduce materials such as germanium, III-Vs and 2D materials together with novel structures such as FinFET. As device scaling continues, parasitic source resistance largely dominated by contact resistance, is beginning to limit the device performance. Specific contact resistivity, ρc, of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height, ΦB, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level, ECNL, resulting in fixed electron and hole Schottky barrier heights ΦBN and ΦBP. High ΦB and low N results in high ρc, eclipsing the promise of intrinsic performance of scaled devices. To obtain low ρc it is essential to reduce ΦB and increase N. Fermi level pinning occurs because wave functions of electrons in the metal tail can decay into the semiconductor in the band gap, creating metal-induced gap states (MIGS). Charging of these states by the metal wavefunction creates a dipole charge causing the Fermi level to align to minimize the dipole charge towards zero, effectively pulling the EF at the interface towards ECNL. Historically the method to reduce ρc is by increasing N to > 1E20/cm3 thereby thinning the barrier, thus allowing more tunneling current. This method works well for n-Si and p-Ge which can be doped heavily. However, it is not very practical for n-Ge, p-Si, many III-Vs and 2D materials because of inability to dope them heavily. Second method is to create an additional dipole at the M-S interface to modulate ΦB by incorporating a dopant or a chalcogen close to the interface to modulate the dipole. Fluorine, sulfur and selenium have been shown to reduce ΦB in many semiconductors. Third method is by inserting a thin interlayer between the metal and semiconductor to depin the Fermi level and reduce ΦB. The metal electron wavefunction now decays in the interlayer resulting in fewer MIGS thus depinning the Fermi level, which now pins on the interlayer. Hence metal workfunction ΦM can now be used to tune the effective barrier height. For n-type ohmic contacts, metals with a low ΦM and interlayer with ~0 conduction band offset (ZnO, TiO2, SnO2) with semiconductor should result in a near zero ΦBN. For p-type ohmic contacts, metals with a high ΦM and insulator with ~0 valence band offset (NiO, CuAlO2) with semiconductor would be desirable. This method has been used to obtain low ΦB and thus low ρc in Si, Ge and III-V semiconductors and should prove to be very useful for 2D materials. Alternatively the interlayer can be chosen such that the metal pins near the band edge to get ~0 ΦB and it can be doped heavily to get thin barrier facilitating increased tunneling. SiGe source/drain in Si PMOS is a good example of this technique. Results of theoretical modeling and experimental work will be presented in this talk.