Source Junction Research Articles

Performance improvement obtained for thin-film transistors fabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 /spl mu/m/10 /spl mu/m TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated.

On the punchthrough phenomenon in submicron MOS transistors

As the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon. A surface diffusion current (I/sub sdif/) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (/spl Delta//spl phi//sub so/). The DIBL effect increases rapidly with decreasing channel length. In addition, the extracted /spl Delta//spl phi//sub so/ from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (/spl ap/0.62 /spl mu/m) to the strong-inversion mode for deep submicron devices (/spl ap/0.12 /spl mu/m). In general, I/sub sdif/ dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (I/sub scl/) as the drain bias increases and the source/drain depletion regions connect. The drain bias for this conversion to occur strongly depends on the channel dimension. Only intermediate submicron devices (/spl ap/0.37 /spl mu/m) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components. For long submicron devices, I/sub sdif/ essentially dominates, while for deep submicron devices, it converts rapidly to I/sub scl/ over the drain bias range investigated. A semi-empirical closed form equation is proposed to describe both I/sub sdif/ and I/sub scl/ and their merging over the entire range of drain bias.

Digital waveguide speech synthesis system and method

A speech synthesizer uses a digital waveguide network to simulate operation of the human pharynx on acoustic signals. One end of the digital waveguide network is connected to a glottal signal source, and another end has a signal filter simulating operation of the acoustic interface at a person's lips. The digital waveguide network has sets of waveguide sections connected in series by junctions, each waveguide section including two digital delay lines running parallel to each other for propagating signals in opposite directions. Each waveguide junction has associated reflection and propagation coefficients. A parameter library that stores sets of glottal source and waveguide junction control parameters for generating corresponding sets of predefined speech signals. The waveguide junction control parameters cause the digital waveguide network to simulate operation of an acoustic tube with a shape corresponding to that of a human pharynx while producing predefined speech sounds. An articulation controller operates the glottal signal source and the digital waveguide network using a sequence of selected sets of said control parameters, thereby causing the synthesizer to generate a specified sequence of speech signals. In a preferred embodiment, the digital waveguide network has three interconnected network branches for simulating operation of the lower pharynx, the oropharynx and the nasopharynx. To generate speech signals corresponding to fricative consonants, the speech synthesizer has noise signal injectors positioned at various points along the digital waveguide network.

Punchthrough currents in sub-micron short channel MOS transistors

The punchthrough current in sub-micron MOS transistors is essentially initiated at the surface near the edge of source junction. A surface diffusion current ( I sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending ( Δφ so). The DIBL effect increases with decreasing channel length. In addition, the extracted Δφ so from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long sub-micron devices (≈0.62 μm) to the strong-inversion mode for deep sub-micron devices (≈0.12 μm). For intermediate sub-micron devices (≈0.37 μm), I sdif eventually converts to the bulk space-charge-limited current ( I scl) as the connected source/drain depletion region expands with increasing drain bias. For long sub-micron devices only I sdif dominates, while for deep sub-micron devices it converts rapidly to I scl in the bulk depletion regions over the drain bias range investigated.

Junction influence on drain current transients in partially-depleted SOI MOSFETs

A model and a numerical-simulation-based demonstration of source and drain junction influence on drain current transients in floating-body partially-depleted (PD) SOI MOSFETs are presented. The investigated transient regime is a Zerbst-type one. It is shown that the junction contribution strongly influences carrier generation processes and therefore affects the accuracy of generation lifetime evaluation when the transistor channel length is reduced. In SOI MOSFETs, the thorough investigation of the contribution of generation processes is essentially two-dimensional.

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

Modeling and 2D Numerical Simulation of Transient Phenomena in Floating Body Soi Mosfets

ABSTRACTThis paper presents a numerical-simulation-based investigation of drain current transients in floating body partially and fully depleted n-channel SOI MOSFETs. For both Zerbst-type and overshoot transients, analytical models are developed and validated. An original contribution concerns the detailed study of drain and source junction influences on the transient regime.

An InSb integrated photo-MOSFET fabricated by photo-enhanced chemical vapour deposition

A new output-controllable InSb infrared (i.r.) detector is proposed. The detector is fabricated by monolithically integrating an InSb p-n junction with an InSb p-channel enhancement mode metal oxide semiconductor field effect transistor (MOSFET). During operation, a photocurrent generated near the source junction is controllably switched to the drain terminal by a gate of the integrated MOSFET. The observed internal quantum efficiency in the ‘on’ state is as high as 85%. Photocurrent on-off ratios are between 260 and 730, improving with increasing channel length. For longchannel devices, the photocurrent in the ‘off’ state is limited by undesired leakage paths. The new structure can be used as an output-controllable i.r. detector.

Carrier transport in amorphous silicon-based thin-film transistors studied by spin-dependent transport.

Carrier transport processes in hydrogenated amorphous silicon-based thin-film transistors (a-Si:H TFT's) are investigated by spin-dependent transport (SDT). Spin-dependent photoconductivity (SDPC) signals arising from less than ${10}^{6}$ spins in a small transistor are detected with an adequate signal-to-noise ratio. SDPC measurements reveal two different limiting steps for the light-induced leakage current in TFT's depending on the gate voltage: bulk recombination in undoped a-Si:H and recombination near the source junction. Also, the leakage current mechanism under high source-drain fields is identified by SDT measurements in the dark as electron hopping via defect states located at the interface between undoped a-Si:H and the passivation silicon nitride layer. Both silicon dangling bonds and nitrogen dangling bonds seem to be involved in the electron hopping process. At temperatures below 100 K, spin-dependent hopping of electrons in conduction-band tail states is observed. The change of the dominant transport path from extended state conduction to variable range hopping conduction with decreasing temperature is confirmed by SDT measurements. \textcopyright{} 1996 The American Physical Society.

Junction metrology by cross-sectional atomic force microscopy

In this article we address practical aspects of the extension of cross-sectional atomic force microscopy to junction metrology. Examining an arsenic (As+) ion implantation split lot, four specimens were epoxied into a single stack. Thus, each sample was exposed to the same preparation conditions. Using a noncontact mode of image acquisition, we verified that a 120 keV implantation resulted in deeper doping profiles than a 35 keV implant. A shift of the source and drain junctions with respect to the gate was also observed as the angle of implant was changed. Correlating the measured junction depths of each sample with secondary-ion-mass spectroscopy profiles, we determined that the detection limit of the junction etch was in the range of 1017–1018 cm−3. The absolute accuracy of this technique was partially limited by tip interaction with the large topography introduced by etching.

Characterization of nonlinear substrate resistance in short-channel MOSFETs

The substrate current conduction in the short-channel MOSFET is described as a virtual JFET coupled with the intrinsic MOSFET. A method to extract the I-V characteristics of the substrate-JFET from I-V measurements on the MOSFET, and pertinent results for a few varied MOSFET structures are presented. The JFET model and characteristics appear valid for the structures investigated, and reveal the fact that modulation by the depletion regions of the source and drain junctions is a major factor in the nonlinearity of the substrate resistance of actual MOSFETs. The nonlinearity of the substrate resistance needs to be considered for an accurate description of the drain-voltage induced limitation of a standard MOSFET. Also, the pinch-off of the substrate-JFET offers a physical explanation to the "early" turn on, a type of drain-voltage limitation present in the short-channel MOSFET when the depletion regions of the source and drain merge in the depth of the channel.

Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling

We have extensively measured and analyzed the current mismatch of a small-size n-channel MOS transistor of 2 /spl mu/m/spl times/2 /spl mu/m operated in weak inversion with its p-well-to-n/sup +/-source junction forward and reverse biased. The case of slightly forward biasing the well-to-source junction represents the action of a gated lateral bipolar transistor in low level injection. The measured dependencies of the mismatch in weak inversion on the back-gate forward and reverse biases have been successfully reproduced by a new simple statistical model. From the experimental data, we suggest that i) subthreshold circuits should be carefully designed for suppression of mismatch arising from back-gate reverse bias, and ii) a gated lateral bipolar action in low level injection may be utilized as a new method of improving the transistor matching.

The effect of focused ion-beam implantation on the threshold voltage of short-channel silicon metal–oxide–semiconductor field-effect transistors

A theoretical modeling of the threshold voltage of short-channel silicon metal–oxide–semiconductor field-effect transistors (MOSFETs) taking into consideration the focused ion-beam technology for the direct implantation of dopants into semiconductor substrates has been performed. Based on a quasitwo-dimensional solution of Poisson’s equation, the surface potential distribution along the channel of a MOSFET has been derived. For this, implanted channel doping concentration is varied linearly along the channel and in a Gaussian-type fashion in a direction perpendicular to the channel. The threshold voltage has been determined from a knowledge of the minimum surface potential in the channel. The effects of finite source and drain junction depths have been included by modifying the depletion capacitance beneath the gate. Short-channel effects on the threshold voltage are thus taken into consideration. The model provides important insight of the physics controling the threshold voltage of a MOSFET. It is noted that a nonuniform doping with density lower in the drain end of the channel and higher in the source end of the channel, and a proper tailoring of the doses, straggles, and energy of implantation are keys to the improvement of the electrical characteristics of a MOSFET.

Fabrication of sub-50-nm gate length n-metal–oxide–semiconductor field effect transistors and their electrical characteristics

A method of fabricating 40-nm gate-length n-metal–oxide–semiconductor field effect transistors (MOSFETs) is described in detail. The fabrication of MOSFETs with gate lengths of this order poses two major problems: how to fabricate such small-geometry gate electrodes, and how to fabricate the ultrashallow source and drain junctions required. Two special techniques are used to overcome these problems: a resist-thinning process using isotropic oxygen plasma ashing for the fabrication of the gate electrodes, and a process of solid-phase diffusion from phosphorus-doped silicated-glass gate sidewalls for fabrication of the source and drain junctions. The resulting 40-nm gate electrodes and ultrashallow 10-nm junctions have an adequate impurity concentration and have been shown to function successfully. It has been confirmed that these 40-nm gate-length n-MOSFETs have good electrical characteristics at room temperature. Certain details of small-geometry MOSFET electrical characteristics are studied using these devices.

Two-Dimensional Analytical Modeling of the Source/Drain Engineering Influence on Short-Channel Effects in SOI MOSFET's

The scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) into the deep-submicron regime increases the influence of source/drain engineering, e.g., the use of a lightly doped source and drain (LDD) structure, on the transistor subthreshold characteristics due to the two-dimensional potential distribution. Device parameters like the subthreshold slope ( S-factor) and the threshold voltage may become dependent on the LDD conditions. This paper presents a theoretical analysis of how source/drain conditions affect the short-channel behavior of fully depleted silicon-on-insulator (SOI) MOSFET's. Accurate two-dimensional analytical modeling which takes into account the non-linear potential variation inside the buried oxide helps elucidate the mechanisms involved. The results, supported by numerical device simulation, indicate that for a correct description in addition to the different built-in potential of the source and drain junctions, an increasing effective channel length with LDD doping reduction must be taken into account.

Suppression of Leakage Current in n-Channel Polysilicon Thin-Film Transistors Using NH3 Annealing

The effect of NH3 annealing on polysilicon thin-film transistors (poly-Si TFT's) is investigated. Substantial reduction of the off-state leakage current in self-aligned n-channel poly-Si TFT's is achieved upon NH3 annealing without degradation of on-state characteristics. NH3 annealing is believed to generate positive fixed charges in the gate oxide near the source and drain junction during NH3 annealing. These positive fixed oxide charges reduce the electric field in the drain junction, resulting in the reduction of the leakage current. NH3 annealing can be applied effectively to fabricate high-performance self-aligned poly-Si TFT's.

A 40 nm gate length n-MOSFET

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-level gate current injections in flash memories initiated by minority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low.

Electrical stressing of submicrometre MOSFETs with raised source/drain structures realised by selective epitaxial growth of silicon using silane only

Submicrometre CMOS devices with raised source and drain (RSD) structures, realised by selective epitaxial growth (SEG) of silicon in silane have been electrically stressed. These devices were less susceptible to hot carrier degradation than their conventional counterparts, due to graded source and drain junctions.

Short channel characteristics of Si MOSFET with extremely shallow source and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 /spl mu/m while punchthrough is suppressed down to 0.07 /spl mu/m, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects. >