Source Electrodes Research Articles

Novel electrical characteristic measurement system of semiconductor films for estimating device characteristics

We proposed a novel measurement method and system to measure the electrical characteristics of non-patterned semiconductor films to estimate the final device’s properties. The proposed method is based on measuring bottom-gate structure thin-film transistor (TFT) using the probe pins as source and drain electrodes. We carefully designed the array structure and material of the probe pin to effectively detect extremely low-level currents without patterned electrodes on the semiconductor film. The contact pressure was also carefully controlled through continuous monitoring using an implemented pressure sensor to ensure the reliability and reproducibility of the measured data. In addition, we developed a method of extracting device parameters, such as the threshold voltage and field-effect mobility, from the measured data, considering the geometric factor of the proposed method. Comparative analysis between the measurement results of the film sample using the proposed system and that of the final TFT sample exhibited similar results with slight deviations. Furthermore, the proposed system provided similar results under repetitive measurements. Consequently, the proposed method and system successfully demonstrated the estimation of the final TFT’s properties by measuring the electrical characteristics of the non-patterned semiconductor film with excellent reliability, highlighting the possibility of effectively reducing costs for development and fabrication.

Negative Differential Resistance Device with High Peak-to-Valley Ratio Realized by Subband Resonant Tunneling of Γ-Valley Carriers in WSe2/h-BN/WSe2 Junctions.

Resonant tunneling diodes (RTDs) are a core technology in III-V semiconductor devices. The realization of high-performance RTD using two-dimensional (2D) materials has been long awaited, but it has yet to be accomplished. To this end, we investigate a range of WSe2/h-BN/WSe2 RTD devices by varying the number of layers of source and drain WSe2. The highest peak-to-valley ratio (PVR) is demonstrated in the three-layer (3L) WSe2/h-BN/1-layer (1L) WSe2 structure. The observed PVR values of 63.6 at 2 K and 16.2 at 300 K are the highest among the 2D material-based RTDs reported to date. Our results indicate the two key conditions to achieve high PVR: (1) resonant tunneling should occur between the Γ-point bands of the source and drain electrodes, and (2) the Γ-point bands contributing to the resonant tunneling should be energetically separated from the other bands. Our results provide an important step to outperform III-V semiconductor RTDs with 2D material-based RTDs.

Design and analysis of central gate organic thin film transistor

Abstract This paper presents a novel central gate organic thin-film transistor (OTFT) with electrodes in top-bottom configuration and its comparative performance analysis with conventional single and dual gate OTFTs. The central gate OTFT is comprised of a single gate electrode configured to be the center thin film. A pair of identical dielectric layers viz. top dielectric layer and a bottom dielectric layer on both sides of gate electrode to facilitate the further deposition top and bottom organic semiconductor layer over them respectively. The organic semiconductor layers (OSC) are configured as top OSC layer and a bottom OSC to accommodate two independent conduction channels. The source and drain electrodes are also deposited in pairs in top and bottom configurations. Due to the subtle modifications in the architecture the resultant output drain current of the central gate (CG) OTFT has increased manifold. It has been found in the study that the CG OTFT produces 94%, 76.36%, 80.58% higher drain current than bottom gate bottom contact (BGBC), top gate bottom contact (TGBC) and bottom gate top contact (BGTC) OTFT respectively of similar size, operating under identical voltage regime. Similarly in the case of dual gate (DG) OTFT an improvement of 5.10% has been recorded without any additional gate electrode at the same operating voltages.

Solution-processed, ultrasensitive, high current density vertical phototransistor using porous carbon nanotube electrode

Multi-wall carbon nanotube (MWCNT) thin film has been identified as the ideal electrode material due to their inherent electronic and optoelectronic properties. We have successfully fabricated a vertical field-effect phototransistor (vFEpT) using MWCNT as a porous source electrode. The optimized MWCNT electrodes showed an electrical conductivity of 3.92 × 103 S/m and a sheet resistance of about 490 Ω/□, with a layer thickness of about 520 nm. The as-fabricated transistor has p-type conductivity because of the unintentional doping of the PbS layer and the intrinsic hole transport property of the MWCNT network. Additionally, the device shows excellent photoelectric performance at 30 mWcm−2 of illumination, with a high current density of 2.3 × 10−3 Acm−2. With a high conductivity network for carrier transfer and separation, the special characteristics of MWCNT nanoporous thin film enable improved photoelectric properties, such as a high photoresponsivity of 3.16 AW−1 and a specific detectivity of 2.33 × 1012 Jones when illuminated at 808 nm light irradiance with an intensity of 0.6 µW/cm2. Furthermore, the device demonstrated a steady dynamic response to an optical signal, with rising and falling times of 31.8 ms and 32.9 ms, respectively. This work presents a new method for creating high-performance vertical phototransistors with MWCNT as the source electrode.

Ion sensors based on organic semiconductors acting as quasi-reference electrodes

Thin-film devices that transduce the chemical activity of ions into electronic signals are essential components in various applications, including healthcare diagnostics and environmental monitoring. Combinations of organic semiconductors (OSCs) and ion-selective materials have been explored for developing solution-processable ion sensors. However, the necessity of reference electrodes (REs) and operational stability in ion-permeable OSCs have posed questions regarding whether reliable measurements with thin-film components are attainable with OSCs. Herein, we report electric double-layer transistors (EDLTs) with OSCs in single-crystal forms for ion sensing. Our EDLTs demonstrated high operational stability, with a one-to-one relationship between the source electrode potential and device resistance, and served as quasi-REs (qRE). When our EDLT is served as qRE, its drift was as small as 0.5 mV/h and comparable to that of commonly employed REs. In our system, the semiconductor-electrolyte interface is self-passivated by the alkyl chains of OSCs in single-crystal structures, with the two-dimensional transport layer appearing unaltered upon gating. EDLT arrays with ion-selective and nonselective liquid junctions enable ion concentration sensing without a conventional RE. These findings provide opportunities to develop thin-film devices based on OSCs for easy integration and reliable measurements.

Effect Evaluation and Modeling of p-Type Contact and p-Well Sheet Resistance of SiC MOSFET with Respect to Switching Characteristics

SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit excellent high-speed switching characteristics. However, the sheet resistance of the p-body region and the contact resistance between the p-body region and source electrode significantly degrade the switching performance. In this study, to clarify the effect of resistance on switching speed, which has not been sufficiently explored before, we used the temperature dependence of sheet and contact resistance and conducted switching tests under different temperature conditions. Furthermore, we created a circuit model that considered body effects and compared the results of the models with the measurements. We were able to reproduce the same temperature and resistance dependences as those exhibited by the experimental results, thus confirming the effectiveness of the model.

An assessment of controlled source EM for monitoring subsurface CO2 injection at the wyoming carbonSAFE geologic carbon storage site

We evaluate if electromagnetic (EM) geophysical methods for monitoring geologic carbon storage (GCS) efforts at the Wyoming CarbonSAFE project adjacent to the Dry Fork Station power plant near Gillette, Wyoming. This first involved acquiring both electric and magnetic fields at eleven different locations ranging in distance from immediately adjacent to 4 km from the plant. Passive EM measurements were made to provide spectral EM noise measurements generated by electricity production at the plant and to determine if useful magnetotelluric (MT) data can be successfully collected in the region. The processed data indicate that useful MT data can be collected as long as the site is located more than 2km away from the power plant as well as active roads and rail lines. Controlled source EM data were collected using three different source configurations, two of which connected to steel casings used to complete the injection wells. Comparing the EM noise measurements to the CSEM data show measurable electric and magnetic field signals at all sites. Next a series of three-dimensional (3D) numerical models were built that simulate resistivity changes caused by the proposed CO2 injection at depths ranging from 2.4 to 3.0km. These models were used to simulate various EM measurement configurations. The modeling shows that casing-source CSEM monitoring can provide sensitivity to the injected CO2 if source electrodes are connected to the bottom of one or both of the injection wells.

High-Performance Proton Field-Effect Transistor Based on Two-Dimensional Cd Vacancy-Resided Cd0.85PS3Li0.15H0.15.

Ion transport is a critical phenomenon underpinning numerous biological, physical, and chemical systems. Proton transistors leveraging proton transport face significant limitations, such as a low on-off ratio and deficient carrier mobility, which restrict their applicability in biological and other scenarios. This study explores the use of two-dimensional (2D) vacancy-residing transition metal phosphorus trichallcogenide-based membranes as the active layer for proton field-effect transistors. The synthesized Cd0.85PS3Li0.15H0.15 membrane exhibits a well-organized layered structure and high hydrophilicity, with nanometer-sized interlayers containing interconnected water networks. These distinct features facilitate proton conduction, leading to a high proton conductivity value of 0.83 S cm-1 at 98% relative humidity and 90 °C, with an activation energy of 0.26 eV. The Cd0.85PS3Li0.15H0.15-based proton transistor demonstrates tunability via gate voltage, thereby enabling effective modulation of proton flow across source and drain electrodes. The transistor notably showcases superior switching characteristics, with an on/off ratio surpassing 5.51 and a carrier mobility of 8.84 × 10-2 cm2 V-1 s-1. The underlying mechanism for this performance enhancement is attributed to electric-field-induced switching in Cd vacancies. This research boosts the development of highly versatile ionotropic devices by introducing advanced 2D ion-conductive membranes.

Constructing and Investigating a Ceria-Based Electro-Chemo-Resistivity Switch

Coupling between an electrochemical reaction and a functional material property has been termed electro-chemo-X, or EC-X, where X can refer to mechanical, optical, magnetic, or thermal properties. Recently, our group has demonstrated a two-terminal electro-chemo-mechanical (ECM) membrane actuator operating under ambient conditions and containing a Ce0.8Gd0.2O1.9 (20GDC) solid electrolyte (SE) layer sandwiched between two Ti oxide/Ce0.8Gd0.2O1.9 (Ti-GDC) nanocomposite thin films. Reducing one nanocomposite film while oxidizing the other was observed to produce reversible volume change thereby driving actuator operation. Here, we use the same electrolyte and nanocomposite layers to further explore the EC-X effect: we present, as proof-of-concept, a functioning, three-terminal, thin film based EC-electrical switching device operating at room temperature.The stacked lamellar structure which comprises the device (Figure 1) was fabricated by first depositing, using magnetron sputtering, a ~200nm thick layer of Ti metal on a sapphire substrate. This was followed by patterning with photolithography and etching, using a commercial, buffered oxide etch solution, thereby creating a 1mm wide channel. The resulting bottom electrode pair ("source" and "drain"), which could be temporarily shorted together when necessary, were subsequently covered by the WB/SE/RV stack, where the same co-sputtered, ~200nm thick Ti-GDC nanocomposite (<40nm grain size; 39at% Ti) was used for both the working body (lower: WB) and the reservoir (upper: RV) layers; a ~400nm thick 20GDC layer served as the SE. Upon WB deposition, the 1mm channel between the source and drain electrodes was filled with the nanocomposite material. The upper electrical contact, a ~200nm Ti layer, covered the RV, and using the same photolithography and etching process already described, the top "gate" electrode was defined. To avoid oxidation of the ion reservoir (RV) surface by atmospheric oxygen during device operation, a ~500 nm thick Ta-oxide layer was deposited by reactive magnetron sputtering and patterned by lift-off techniques.We find that following two hours application of -/+ 6V bias between the "gate" and (temporarily shorted) "source" / "drain" electrodes under ambient conditions, the average change in ohmic resistance of the WB in the 1mm channel upon reversal of electrode bias was determined, by cyclic voltammetry between the source and drain electrodes, to be 6.5 ±1.8Gohm with statistical uncertainty based on at least 3 cycles, 5 samples. Negative "gate" bias produced the lower resistance values. The low resistance state decayed during approx. 24 hours, as monitored by cyclic voltammetry. Raising the temperature above ambient (333K) further reduced resistance. We interpret these observations as follows: Negative bias voltage application to the "gate" produces a gradient of the chemical potential of diffusing oxygen ions at the SE-WB interface. This gradient leads to the injection of ions into the WB, thereby promoting an electrochemical oxidation reaction. The nanocomposite in the 1mm channel decays from the more highly conductive state during approximately twenty-four hours. Reversing the bias polarity extracts ions from the WB, with the opposite results. To complement the findings of the E-field promoted oxidation, we performed annealing at 633K for 23 hours in air of a device which lacked the SE/RV/"gate" electrode/Ta-oxide layers, i.e. the WB was uncovered. We observed an increase of two orders of magnitude in the conductivity of the nanocomposite in the 1mm channel, which then relaxes with time. As a control, the same thermal treatment was conducted under vacuum. In this case no change was observed in channel conductivity.A possible explanation for how oxidation increases the Ti-GDC nanocomposite conductivity may be found in a suitable variant of the space charge model [1, 2]. We note that nanocrystallinity introduces such a high density of interfaces/grain boundaries that total conductivity may become interfacially controlled. Grain boundaries in doped ceria lack long range order and are relatively rich in oxygen vacancies (VO) and Ce3+, which, along with a space charge zone which forms for charge neutrality, produce a blocking effect for ion conduction. Oxidation of Ce3+ => Ce4+ leads to a lowering of total real charge, causing the spatial extent of the space charge zone to shrink as well. Finally, this succeeds in lowering the potential barrier for ion diffusion across the grain boundary, which increases the overall conductivity. Reduction of the Ti-GDC nanocomposite produces the opposite effect.[1] S. K. Kim, S. Khodorov, I. Lubomirsky, S. Kim, Phys Chem Chem Phys 2014, 16, 14961, https://doi.org/10.1039/c4cp01254b[2] S. Kim, J. Maier, J. Elecrochem. Soc. 2002, 149, J73, https://doi.org/10.1149/1.1507597 Figure 1

CMOS-Compatible Single-Gated Memtransistor Having 3-D Bulk Channel Embedded with Quantum Well Memory Nodes for Fast Training of Deep Neural Network

Recently, three-terminal synaptic devices having gate, source, and drain electrodes have been actively researched to compensate for the poor reliability of two-terminal synaptic devices such as resistive random access memory (ReRAM) and phase change random access memory (PCRAM)1. Two-terminal devices inherently suffer from read disturbance problems, where the stored resistance state changes gradually during the read process of the artificial neural network2. In addition, two-terminal devices essentially require selection devices for performing the write (program or erase) and read process, which is limited to commercialization because matching of the electrical characteristics between the selection device and the synaptic device was extremely difficult3. Moreover, the training speed of artificial neural networks would degrade due to the constant on/off ratio of conductance of two-terminal synaptic devices.To solve this problem, the memtransistors that can change the conductance range of the channel with gate bias have been reported. However, most of the reported memtransistors employed 2-D materials such as MoS2, WSe2, and SnS2 as a channel layer, which is a limitation for uniform large-area thin film growth4–6. In other words, the memtransistors with a 2-D channel layer do not have CMOS compatibility.In this study, for the first time, we designed a CMOS-compatible single-gated memtransistor having an indium-gallium-zinc-oxide (IGZO) channel embedded with quantum well memory nodes via Au nanoparticles. The quantum well memory nodes were obtained by precisely designing the diameter of Au nanoparticles in the IGZO 3-D bulk channel and SiO2 gate oxide interfaces. In addition, the quantum well memory nodes using Au nanoparticles were investigated by an energy band diagram obtained from ultraviolet photoelectron spectroscopy (UPS) analysis of Au, IGZO, and Al source/drain electrodes. Thereby, the gate-tunable pinched hysteresis loops in the output curve of the designed memtransistor were achieved ranging from -30 to 30 V, which present channel conductance tuning by controlling the amplitude of gate bias. In addition, the gate-tunable synaptic plasticities (i.e., long-term potentiation (LTP) and long-term depression (LTD)) were obtained by changing the amplitude of gate bias from 10.0 to 13.5 V at an incremental of 0.5 V, exhibiting exponential growth of maximum channel conductance depending on the amplitude of gate bias. Finally, we demonstrated the fast training of the hardware-based deep neural network simulation using the gate-tunable synaptic plasticity of the designed memtransistor. The mechanism of single-gated memtransistor having quantum well memory nodes via Au nanoparticles and its application will be presented in detail. Acknowledgement This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. RS-2023-00260527) and Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2023)-RS-2023-00253914) grant funded by the Korea government(MSIT)" References Fuller, E. J. et al. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science (80-. ). 364, 570–574 (2019).Yoon, J., Chang, M. & Khwa, W. Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. Jssc 57, 1–13 (2022).Kim, H. J. et al. Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array. Adv. Mater. 2203643, (2022).Lee, H. S. et al. Dual-Gated MoS2 Memtransistor Crossbar Array. Adv. Funct. Mater. 30, 1–12 (2020).Ding, G. et al. Reconfigurable 2D WSe2-Based Memtransistor for Mimicking Homosynaptic and Heterosynaptic Plasticity. Small 17, 1–13 (2021).Rehman, S., Khan, M. F., Kim, H. D. & Kim, S. Analog–digital hybrid computing with SnS2 memtransistor for low-powered sensor fusion. Nat. Commun. 13, 1–8 (2022). Figure 1

Investigation of Neuromorphic Behaviors in Access Regions-Integrated Van Der Waals Heterostructures

The emergence of neuromorphic devices has disrupted the traditional von Neumann architecture, providing a solution to the challenges of simulating neural parallel processing and power consumption in conventional computer architectures [1]. Access regions (ARs) are strategically created and positioned in proximity to source and drain electrodes, resulting in a channel that does not overlap with the floating gate (FG) [2]. In this study, we investigated ARs integrated van der Waals heterostructural field-effect transistor (AR-VH-FET) device, constructed by vertically stacking several 2D materials. Specifically, molybdenum disulfide (MoS2) served as a channel, hexagonal boron nitride (h-BN) as a tunneling layer, and graphene (Gr) as the FG. We conducted measurements on the transfer and output characteristics to characterize the electrical performance of the AR-VH-FET. Under a fixed VDS, with the application of positive and negative VBG as programming and erasing voltages respectively, we measured device retention and endurance. AR-VH-FET devices not only emulate basic neuromorphic functions but also replicate biological characteristics.

Modulating Neuromorphic Behavior of Organic Synaptic Electrolyte-Gated Transistors Through Microstructure Engineering and Potential Applications.

Organic synaptic transistors are a promising technology for advanced electronic devices with simultaneous computing and memory functions and for the application of artificial neural networks. In this study, the neuromorphic electrical characteristics of organic synaptic electrolyte-gated transistors are correlated with the microstructural and interfacial properties of the active layers. This is accomplished by utilizing a semiconducting/insulating polyblend-based pseudobilayer with embedded source and drain electrodes, referred to as PB-ESD architecture. Three variations of poly(3-hexylthiophene) (P3HT)/poly(methyl methacrylate) (PMMA) PB-ESD-based organic synaptic transistors are fabricated, each exhibiting distinct microstructures and electrical characteristics, thus serving excellent samples for exploring the critical factors influencing neuro-electrical properties. Poor microstructures of P3HT within the active layer and a flat active layer/ion-gel interface correspond to typical neuromorphic behaviors such as potentiated excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and short-term potentiation (STP). Conversely, superior microstructures of P3HT and a rough active layer/ion-gel interface correspond to significantly higher channel conductance and enhanced EPSC and PPF characteristics as well as long-term potentiation behavior. Such devices were further applied to the simulation of neural networks, which produced a good recognition accuracy. However, excessive PMMA penetration into the P3HT conducting channel leads to features of a depressed EPSC and paired-pulse depression, which are uncommon in organic synaptic transistors. The inclusion of a second gate electrode enables the as-prepared organic synaptic transistors to function as two-input synaptic logic gates, performing various logical operations and effectively mimicking neural modulation functions. Microstructure and interface engineering is an effective method to modulate the neuromorphic behavior of organic synaptic transistors and advance the development of bionic artificial neural networks.

Graphene-Based Field-Effect Photodetector with HgCdTe Absorber

A field-effect photodetector structure composed of an Al2O3-encapsulated bilayer graphene conductive channel attached to an Al2O3 dielectric layer deposited on a HgCdTe absorbing layer on CdTe/Si <211> was studied. Ti/Au ohmic contacts to the graphene layer were used as drain and source electrodes and back-gate voltage was applied to the Si substrate. It was demonstrated that 80% and 10% modulation of the graphene channel conductivity can be achieved under blue (50 W/cm2) and infrared (IR) (0.02 W/cm2) illumination, respectively, at a gate voltage of 7 V. Detector responsivity was measured as 406 A/W and 1.83 A/W under IR lamp and 405-nm laser irradiation, respectively, with corresponding gain values of 340 and 5.6. The detectivity of the 4 × 4 photodetector arrays was on the order of 1010 Jones for the mid-wave infrared wavelength range (3–5 μm).

A nanoscale photonic thermal transistor for sub-second heat flow switching

Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VOx)-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

Automated Scanning Dielectric Microscopy Toolbox for Operando Nanoscale Electrical Characterization of Electrolyte‐Gated Organic Transistors

AbstractElectrolyte‐gated organic transistors (EGOTs) leveraging organic semiconductors' electronic and ionic transport characteristics are the key enablers for many biosensing and bioelectronic applications that can selectively sense, record, and monitor different biological and biochemical processes at the nanoscale and translate them into macroscopic electrical signals. Understanding such transduction mechanisms requires multiscale characterization tools to comprehensively probe local electrical properties and link them with device behavior across various bias points. Here, an automated scanning dielectric microscopy toolbox is demonstrated that performs operando in‐liquid scanning dielectric microscopy measurements on functional EGOTs and carries out extensive data analysis to unravel the evolution of local electrical properties in minute detail. This paper emphasizes critical experimental considerations permitting standardized, accurate, and reproducible data acquisition. The developed approach is validated with EGOTs based on blends of organic small molecule semiconductor and insulating polymer that work as accumulation‐mode field‐effect transistors. Furthermore, the degradation of local electrical characteristics at high gate voltages is probed, which is apparently driven by the destruction of local crystalline order due to undesirable electrochemical swelling of the organic semiconducting material near the source electrode edge. The developed approach paves the way for systematic probing of EGOT‐based technologies for targeted optimization and fundamental understanding.

Strain-Sensor-In-Pixel Technology for Resolution-Sustainable Stretchable Displays.

One of the limitations of stretchable displays is the severe degradation of resolution or the decrease in the number of pixels per unit area when stretched. Hence, we suggest a strain-sensor-in-pixel (S-SIP) system through the adoption of hidden pixels that are activated only during the stretch mode for maintaining the density of on-state pixels. For the S-SIP system, the gate and source electrodes of InGaZnO thin-film transistors (TFTs) in an existing pixel are connected to a resistive strain sensor through the facile and selective deposition of silver nanowires (AgNWs) via electrohydrodynamic-jet-printing. With this approach, the strain sensor integrated TFT functions as a strain-triggered switch, which responds only to stretching along the designated axes by finely tuning the orientation and cycles of AgNW printing. The strain sensor-integrated TFT remains in an off-state when unstretched and switches to an on-state when stretched, exhibiting a large negative gauge factor of -1.1 × 1010 and a superior mechanical stability enduring 6000 cycles, which enables the efficient structure to operate hidden pixels without requiring additional signal processing. Furthermore, the stable operation of the S-SIP in a 5 × 5-pixel array is demonstrated via circuit simulation, implying the outstanding applicability and process compatibility to the conventional active-matrix display backplanes.

Transient thermal 2D FEM analysis of SiC MOSFET in short-circuit operation including high-temperature material laws and phase transition of aluminum source electrode

Understanding the electrothermal behavior of SiC MOSFET power devices under extreme operation conditions, such as short circuits, is crucial for their application certification. However, simulating short circuits in electronic components is challenging due to the necessity of a comprehensive thermal and electrical Multiphysics model that incorporates material laws and respects elevated temperatures with broad ranges. It is also needed to model the melting of the topside Al electrode. The paper presents for the first time a 2D electrothermal FEM that simulates the thermodynamic behavior of SiC MOSFET at high temperatures transistors under short-circuit conditions, including wide-range temperature-dependent material property laws. This work models the Al phase transition by considering the apparent heat capacity method and including the latent heat absorbed during the Al solid-liquid phase change (PC). The geometric accuracy of this study provides significant added values compared to existing 1D models. It was deduced that including the temperature-dependent material laws highly impacted the results. The rise in SiC junction temperature led to a delay in the onset of Al melting. It also impacted the progression manner of the Al melting process after the formation of new melting fronts.

Ambipolar Charge Injection and Bright Light Emission in Hybrid Oxide/Polymer Transistors Doped with Poly(9‐Vinylcarbazole) Based Polyelectrolytes

AbstractLight‐emitting transistors (LETs) are a remarkable, emerging class of electronic devices that combine the switching function of field‐effect transistors (FETs) and the light‐emitting function of light‐emitting diodes (LEDs). In order to achieve efficient light emission, effective electron and hole injection from source and drain electrodes is necessary. Various strategies have been introduced to accomplish this, such as incorporating asymmetric electrodes or charge injection layers during device fabrication. These approaches have inevitably introduced complexity in the device fabrication process. Herein, light‐emitting electrochemical transistors (LECTs) are demonstrated that combine principles of electrochemistry and optoelectronics to achieve multi‐functionality in a simple device architecture. Hybrid polyelectrolytes, poly(9‐vinylcarbazolesulfonate)‐ lithium and copper (II) salts (PVK‐Li and PVK‐Cu) incorporating Li+ ion and Cu2+ ions are added at variable concentrations to the organic emitting layer of LECTs to effect electrochemical p‐type doping. This electrochemical doping approach yielded improvements in electrical and optical performances including mobilities, brightnesses, and external quantum efficiency of the LECTs. The dynamics of how charges including ions, electrons, and holes move and interact are discussed in the device to facilitate emissive charge carrier recombination and light emission. This investigation provides valuable insights into the realms of both electrochemistry and optoelectronics.

Field Induced Off‐State Instability in InGaZnO Thin‐Film Transistor and its Impact on Synaptic Circuits

AbstractCharge storage synaptic circuits employing InGaZnO thin‐film transistors (IGZO TFTs) and capacitors are a promising candidate for on‐chip trainable neural network hardware accelerators. However, IGZO TFTs often exhibit bias instability. For synaptic memory applications, the programming transistors are predominantly exposed to asymmetric off‐state biases, and a unique field‐dependent on‐current reduction under off‐scenario is observed which may result in programming current variation. Further examination of the phenomenon is conducted with transmission line‐like method and degradation recovery tests, and current reduction can be attributed to contact resistance increase by charge trapping in the source and drain electrode and the channel region. The current decrease is subsequently formulated with a stretched exponential model with bias‐dependent parameters for quantitative circuit analysis under off‐state degradation. A neural network hardware acceleration simulator is utilized to assess the complicated impact the off‐state current degradation could instigate on on‐chip trainable IGZO TFT‐based synapse arrays. The simulation results generally demonstrate deteriorated training accuracy with aggravated off‐state instability, and the accuracy trend is elucidated from the perspective of weight symmetry point.

Functionalized MXene ink enables environmentally stable printed electronics

Establishing dependable, cost-effective electrical connections is vital for enhancing device performance and shrinking electronic circuits. MXenes, combining excellent electrical conductivity, high breakdown voltage, solution processability, and two-dimensional morphology, are promising candidates for contacts in microelectronics. However, their hydrophilic surfaces, which enable spontaneous environmental degradation and poor dispersion stability in organic solvents, have restricted certain electronic applications. Herein, electrohydrodynamic printing technique is used to fabricate fully solution-processed thin-film transistors with alkylated 3,4-dihydroxy-L-phenylalanine functionalized Ti3C2Tx (AD-MXene) as source, drain, and gate electrodes. The AD-MXene has excellent dispersion stability in ethanol, which is required for electrohydrodynamic printing, and maintains high electrical conductivity. It outperformed conventional vacuum-deposited Au and Al electrodes, providing thin-film transistors with good environmental stability due to its hydrophobicity. Further, thin-film transistors are integrated into logic gates and one-transistor-one-memory cells. This work, unveiling the ligand-functionalized MXenes’ potential in printed electrical contacts, promotes environmentally robust MXene-based electronics (MXetronics).