Source-drain Spacing Research Articles

A Novel GaAs/InGaAs/AlGaAs Structure of Modulation-DopedField-Effect Transistors with High Transconductances

Novel structure GaAs/InGaAs/AlGaAs pseudomorphicmodulation-doped field-effect transistors (MODFETs) with a buried p-i-n dipolelayer and a 200 nm buffer layer have been fabricated. According tothe calculation, the dipole buried layer not only results in the very thinbuffer layer required, but also enhances the density of two-dimensionalelectron gas. The measured transconductances of these MODFETs, with a gatelength of 2 µm and a drain-source spacing of 5 µm, are as high as320 mS/mm and the measured maximum drain currents of the typical devices arehigher than 500 mA/mm.

Field Effect Transistor with Self-Organized In0.15Ga0.85As/GaAs Quantum Wires as a Channel Grownon (553)B GaAs Substrates

A functional field effect transistor with self-organizedIn0.15Ga0.85As/GaAs quantum wires (QWRs) as a channel was achievedby molecular beam epitaxy on a (553)B GaAs substrate. Both thethree-dimensional image of atomic force microscopy and the polarization of thephotoluminance peaks reveal that the channel of the device is aself-organized QWR structure. The device with a gate length of 2 µm anda source-drain spacing of 5 µm performed a good enhancement-modecharacteristic and a maximum transconductance of 65 mS/mm was obtained atthe gate voltage of 1.0 V by the geometric gate width at room temperature.The saturated drain current is as high as 5.6 mA. The device exhibited amuch larger current capacity due to the high density of the self-organizedQWRs in its channel layer. In addition, the effective gate width wasdiscussed in comparison with the geometric gate width of the device, fromwhich a larger maximum transconductance of 130 mS/mm could be estimated.

GaAs/InGaAS/AlGaAs MODFETs with a very thin buffer layer and very high transconductances

Novel structure GaAs/InGaAS/AlGaAs pseudomorphic MODFETs with a p–i–n dipole buried layer and a 200 nm buffer layer have been fabricated with molecular beam epitaxy and regular wet etching processing technology. The measured transconductance of these MODFETs, with a gate length of 2 μm and a drain-source spacing of 5 μm, are as high as 320 mS/mm. The measured maximum drain currents of the typical devices are higher than 500 mA/mm. As far as we know, these represent the best results ever reported for MODFETs with similar scales

GaN/AlGaN HEMTs operating at 20 GHz withcontinuous-wave power density > 6 W/mm

MBE-grown GAN/AlGaN HEMTs have been fabricated on a 2" SiC wafer, where the source-drain spacing was 2 µm and the gate length was 0.15 µm. A peak extrinsic transconductance of 350 mS/mm and a maximum drain current density greater than 1.5 A/mm were obtained. Small-signal S-parameter measurement showed fT of 85 GHz and fMAX approaching 140 GHz. At 20 GHz, a continuous-wave output power density of 6.6 W/mm was obtained with power-added-efficiency (PAE) of 35%, yielding the highest reported power performance at 20 GHz.

Design and characteristics of n-channel insulated-gate field-effect transistors

An n-channel insulated-gate field-effect transistor technology established at IBM Research has served as the basis for further development leading to FET memory. Designs and characteristics of experimental devices of 500 and 1000 A gate insulator thicknesses are presented, with particular attention to the effects of source-drain spacing.

155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators

We report on the design and measurement of monolithic 155- and 213-GHz quasi-optical oscillators using AlInAs/GaInAs/InP HEMT's. These results are believed to be the highest frequency three-terminal oscillators reported to date. The indium concentration in the channel was 80% for high sheet charge and mobility. The HEMT gates were fabricated with self-aligned sub-tenth-micrometer electron-beam techniques to achieve gate lengths on the order of 50 nm and drain-source spacing of 0.25 /spl mu/m. Planar antennas were integrated into the fabrication process resulting in a compact and efficient quasioptical Monolithic Millimeter-wave Integrated Circuit (MMIC) oscillator. >

Study of the dependence of Ga/sub 0.47/In/sub 0.53/As/Al/sub x/ In/sub 1-x/As power HEMT breakdown voltage on Schottky layer design and device layout

Summary form only given. A systematic study of the improvement of Ga/sub 0.47/In/sub 0.53/As/Al/sub x/ In/sub 1-x/As HEMT (high electron mobility transistor) breakdown voltage by varying the Schottky layer design and device geometry is presented. The HEMT structure investigated is a modulation-doped Ga/sub 0.47/In/sub 0.53/As/Al/sub x/ In/sub 1-x/As on InP device with a sheet of charge placed at the center of the 300 AA wide channel. The device with a gate length of 0.5 mu m, a source-drain spacing of 5 mu m, and an Al/sub 0.7/In/sub 0.3/As Schottky layer exhibited the best breakdown characteristics of mod BV/sub gd/ mod =6.8 V and BV/sub ds/=7.8 V. The typical transistor had a maximum transconductance of 500 mS/mm, a full channel current of 700 mA/mm for a gate bias of 0.4 V, and a current gain cutoff frequency of over 80 GHz. The power performance was measured on 500- mu m-wide devices at 4 GHz and V/sub ds/=4.5 V. Under Class AB operating conditions, the output power density, power-added efficiency, and power gain were 0.45 W/mm, 59%, and 14.25 dB, respectively. >

Submicron-gate InP power MISFET's with improved output power density at 18 and 20 GHz

The microwave characteristics at 18 and 20 GHz of submicron-gate indium phosphide (InP) metal-insulator-semiconductor field-effect transistors (MISFETs) for high output power density applications are presented. InP power MISFETs were fabricated with 0.7 mu m gate lengths, 0.2 mm gate widths, and drain-source spacings of 2, 3 and 5 mu m. The output power density was investigated as a function of drain-source spacing. The best output power density and gain were obtained for drain-source spacings of 3 mu m. At 18 GHz output power densities of 1.59 W/mm with a gain of 3.47 dB and a power-added efficiency of 20.0% were obtained for a drain-source spacing of 3 mu m. At 20 GHz output power densities of 1.20 W/mm with a gain of 3.17 dB and a power-added efficiency of 13.6% were obtained for a drain-source spacing of 3 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs heterostructure FET frequency dividers fabricated with high-yield 0.5/μm direct-write trilevel-gate-resist

Frequency dividers and FET test structures have been fabricated on selectively doped n+-AlGaAs/GaAs heterostructure FETs (HFETs) with 0.5 μm gate length electron-beam direct writing on a novel trilevel resist, EBR-9/Ge/PMGI. A divide-by-two master-slave frequency divider fabricated with direct-coupled FET logic gates operated up to 9.3 GHz. The input frequency range of a divide-by-two transmission-gate frequency divider was from 3.2 to 12.2 GHz, with a supply voltage of 1.2 V at room temperature. The average propagation delay (fan-in and fan-out = 1) was 18.2ps/gate, with a power dissipation of 3.9 mW/stage. With a 3.5 μm source-drain spacing, a peak transconductance of 360mS/mm was measured. The functional yield of both discrete devices and circuits was 92% across 2 in-diameter wafers.

P-channel quantum-well heterostructure MI/sup 3/SFET

A p-channel heterostructure MISFET-like device based on a quantum well with an underlying impurity layer is discussed. The device is based on an AlGaAs/GaAs heterostructure with a recessed-gate geometry and uses Zn-diffused refractory-metal contacts. The 4100 cm/sup 2//V-s hole mobility obtained in this inverted-interface structure at 77 K is comparable to that achieved in normal-interface AlGaAs/GaAs heterostructures. Transconductance and K-factor values as high as 52 mS/mm and 140 mS/V-mm, respectively, are obtained at 77 K in p-channel FETs with 2.0- mu m gate lengths and 6.0- mu m source-drain spacings, representing state-of-the-art values for p-HFETs at similar dimensions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gold-germanium-based ohmic contacts to the two-dimensional electron gas at selectively doped semiconductor heterointerfaces

Results of a study of ohmic contacts to the two-dimensional electron gas (2DEG) at N+-n III-V semiconductor heterointerfaces are presented. In a comparison of alloyed metallizations based on the Au-27at. %Ge eutectic system, the addition of Ni and the method of deposition were found to have the largest effects in lowering the contact resistance. The Ni-Ge-Au Ohmic contact reproducibly gives a (width-normalized) contact resistance of less than 0.2 Ω . mm, which is adequate for MESFET applications using these structures. MESFET's fabricated with (Al,Ga) As and (Al,In,Ga) As heterojunction 2DEG channels and Ni-Ge-Au contacts have source-drain resistances (R sd ), which decrease dramatically at low temperature as a result of the mobility enhancement in the 2DEG channel and the small contribution of contact resistances. The transconductance (g m ) of the device thus more nearly approaches its high intrinsic value. At 77 K, the best (Al,Ga) As FET's had R sd = 0.69 Ω . mm and g m = 309 mS/mm with gate lengths of 1.5 µm and a source-drain spacing of 9 µm. A microwave gain of 11 dB at 6.4 GHz has been obtained at room temperature for these devices.

Characterization of InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</inf> As/Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.15</inf> - Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.85</inf> As ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.05 \le y \le 0.2</tex> ) MODFET's grown by MBE have been characterized at dc (300 and 77 K) and RF frequencies. Transconductances as high as 310 and 380 mS/mm and drain currents as high as 290 and 310 mA/mm were obtained at 300 and 77 K, respectively, for 1-µm gate lengths and 3-µm source-drain spacing devices. Lack of persistent trapping effects, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> collapse, and threshold voltage shifts observed with these devices are attributed to the use of low mole fraction Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</inf> As while still maintaining 2DEG concentrations of about 1.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . Detailed microwave S-parameter measurements indicate a current gain cut-off frequency Of 24.5 GHz When <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y = 0.20</tex> , which is as much as 100 percent better than similar GaAs/AlGaAs MODFET structures, and a maximum frequency of oscillation of 40 GHz. These superior results are in part due to the higher electron velocity of InGaAs as compared with GaAs. Velocity field measurement performed up to 3 kV/cm using the magnetoresistance method indicates an electron saturation velocity of greater than 1.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s at 77 K for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y = 0.15</tex> , which is 20 percent higher than GaAs/AlGaAs MODFET's of similar structure.

Selectively doped heterostructure frequency dividers

The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having 1-µm gate lengths and 4-µm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al .3 Ga .7 As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.

Channel-length effects in quarter-micrometer gate-length GaAs MESFET's

The electrical performance of 0.25-µm gate-length GaAs MESFET's with channel lengths (i.e., source-drain spacings) of 2.1 and 0.5µm is compared. An extremely short channel length has been found experimentally to lead to significant increases in the electron average drift velocity, transconductance, and forward transducer gain. Increases in both the electron average drift velocity and intrinsic dc transconductance of ∼70 percent were observed in these 0.25-µm gate-length devices when the source-drain spacing was reduced from 2.1 to 0.5µm. Deleterious effects such as increased output conductance and interelectrode capacitances were also noted.

Short-channel effects in 0.5-µm source-drain spaced vertical GaAs FET's—A first experimental investigation

The output characteristics of vertical GaAs MESFET's with a 0.5 µm source-drain spacing are discussed. It is found that the measured pinch-off voltage is substantially larger than the one expected from the geometrical Schottky diode pinch-off, and current limiting surface depletion effects are not observed.

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

5 GHz binary frequency division on GaAs

A fully planar self-aligned technology with a standard photolithographic process has been used to fabricate binary frequency dividers on GaAs counting correctly from d.c. to over 5 GHz, which is the best performance so far on such circuits. The divider is an optimised version of the gated T master/slave flip-flop. The m.e.s.f.e.t.'s gates are 0.6 μm within 2 μm drain-source spacing.

A two-dimensional simulation of a cooled, submicrometer indium arsenide Schottky-gate FET

A two-dimensional simulation of an InAs, Schottky-gate FET operated at 77 K is reported. A device of 0.25-µm source-drain spacing is assumed. The full field-dependent mobility is treated. The results suggest that such a device would have performance characteristics comparable even to Josephson junctions for high-speed low-power logic applications.

Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.