Drain-source Breakdown Voltage Research Articles

A thorough study on the electrical performance change and trap evolution of AlGaN/GaN MIS-HEMTs under proton irradiation

In this work, the effects of proton-induced trap evolution on the electrical performances of AlGaN/GaN metal–insulator–semiconductor (MIS) high-electron-mobility-transistors (HEMTs) have been investigated in detail. Contrary to observed proton-induced degradation in sheet electron density (ns), carrier mobility (μn), and sheet resistance (RSH), a significant improvement in gate leakage current (IG) and off-state drain–source breakdown voltage (BVDS) is found in irradiated devices. The low-frequency noise (LFN) results show that the density of traps in the AlGaN layer and AlGaN/GaN interface increases after irradiation, which leads to a degradation in ns, μn, and RSH and an improvement in BVDS due to enhanced electron trapping and depletion. Furthermore, the measurement results obtained from the frequency-dependent conductance technique show that irradiated devices exhibit decreased trap density (DT) at the insulator/semiconductor interface with hardly changed trap energy level (ET), which confirms the observed proton-induced decrease in IG. An increase in DT at the AlGaN/GaN interface is also found after irradiation, which is consistent with LFN results. These traps with deeper ET induce a serious Coulomb scattering effect. This work provides valuable information for the systematic understanding of the proton irradiation effect of AlGaN/GaN MIS-HEMTs.

Investigations on Wide-Gap Al0.21Ga0.79N Channel MOS-HFETs With In0.12Al0.76Ga0.12N Barrier/Buffer and Drain Field-Plate

This work investigates, for the first time, wide-gap Al0.21Ga0.79N channel metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with In0.12Al0.76Ga0.12N barrier/buffer and drain field-plate (DFP) designs. High-k and wide-gap Al2O3 was grown as the gate oxide and surface passivation by using non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. A control device having the same epitaxial layers, except with In0.12Al0.88N barrier/buffer was studied in comparison. Enhanced spontaneous polarization effect, improved interfacial quality, and enhanced carrier confinement have been achieved by using the In0.12Al0.76Ga0.12N barrier/buffer design, which has successfully resulted in improved carrier transport, increased electron concentration, and high current densities. The present In0.12Al0.76Ga0.12N/AlN/Al0.21Ga0.79N MOS-HFET design with (without) DFP design has demonstrated superior maximum drain-source current density (IDS, max) of >1 (>1) A/mm at VDS = 20 V, high saturated drain-source current density at VGS = 0 V (IDSS0) of 791.1 (755) mA/mm, and low specific on-resistance (Ron, sp) of 2.83 (2.81) mΩ/cm2. High device figure-of-merit (FOM) on BVDS2/Ron, sp of 93.7 (75.4) MW/cm2 was also obtained with the three-terminal on-state drain-source breakdown voltage (BVDS) of 515 (460) V. The present design is promisingly advantageous to high-current and high-voltage power-switching circuit applications.

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are switching in a space environment. In this study, the total ionizing dose (TID) responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz. A significant shift was observed in the threshold voltage as the frequency increased, which resulted in premature failure of the drain–source breakdown voltage and drain–source leakage current. The degradation is attributed to the high activation and low recovery rates of traps at high frequencies. The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.

AlGaN/AlN/SiC Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with Al2O3 Gate-Oxide and Step-Graded AlGaN Channel

Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs), grown on a SiC substrate, with step-graded Si-doped (n = 3 × 1018 cm-3) widegap AlxGa1-xN channel and Al2O3 gate-dielectric are investigated. Increased Al-compositions with x = 0.25, 0.5, and 0.75 towards the buffer were devised in the composite widegap channel. The high-k Al2O3 dielectric/passivation layer was grown by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. Experimental comparisons were made with respect to a conventional Schottky-gate HFET.The epitaxial structure of the studied Al2O3-dielectric Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN MOS-HFET (sample A) and Schottky-gate HFET (sample B). Both devices have the identical epitaxial structure grown on a SiC substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. The layer structure includes an undoped AlN buffer, a 20-nm undoped Al0.75Ga0.25N barrier, a 150-nm step-graded Si-doped (n = 3 × 1018 cm-3) AlxGa1-xN channel (x = 0.25, 0.5, and 0.75), and a 20-nm undoped Al0.75Ga0.25N barrier. Standard photolithography and lift-off techniques were used for device processing. For sample B, mesa etching was performed with respect to a 100-nm thick Ni barrier by using an inductively coupled-plasma reactive ion etcher (ICP-RIE). Flow rates were tuned and set at 10 sccm and 20 sccm for the mixed etching gases of BCl3 and Cl2, respectively. The 20-nm undoped Al0.75Ga0.25N barrier was etched away before deposition of source/drain electrodes. Ti (10 nm)/Al (50 nm)/Ni (10 nm)/Au (50 nm) were evaporated. The source/drain ohmic contacts were formed by annealing the sample for 25 seconds at 900°C by using a rapid thermal annealing (RTA) system (ULVAC MILA-5000). Then, 30-nm thick Al2O3 layer was deposited on the Al0.75Ga0.25N barrier by using the USPD technique. Finally, gate electrode of Ni (100 nm)/Au (50 nm) was evaporated after gate photolithography. As for sample A, the gate electrode was formed directly on the surface of Al0.75Ga0.25N barrier without oxide deposition.Improved device performance of the present MOS-HFET design have been obtained, including maximum drain-source current density (IDS, max ) of 130.1 A/mm at VGS = 10 V and VDS = 20 V, IDS at VGS = 0 V (IDSS0 ) of 83.1 mA/mm, on/off-current ratio (Ion /Ioff ) of 1.4 × 107, maximum extrinsic transconductance (gm, max ) of 11.8 mS/mm, two-terminal off-state gate-drain breakdown voltage (BVGD ) of -404 V, and three-terminal on-state drain-source breakdown voltage (BVDS ) of 364 V at 300 K. The present MOS-HFET design has also shown high spectral responsivity (SR) of 737 A/W under 250-nm deep-UV radiation at 300 K.

Improved Electrical and Deep-UV Sensing Characteristics of Al2O3-Dielectric AlGaN/AlN/SiC MOS-HFETs

Improved electrical and deep-UV sensing characteristics of Al2O3-dielectric Al0.75Ga0.25N/n-AlxGa1−xN/Al0.75Ga0.25N/AlN metal-oxide-semiconductor hetero-structure field-effect transistors (MOS-HFETs), grown on a SiC substrate, with an AlGaN ultra-widegap channel design are investigated. 30 nm thick high-k Al2O3 was deposited as both the gate oxide and surface passivation layer by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. Improved device characteristics, including maximum drain-source current density (IDS,max) of 130.1 mA mm−1, maximum extrinsic transconductance (gm,max) of 11.8 mS mm−1, on/off-current ratio (Ion/Ioff) of 1.4 × 107, gate-voltage swing (GVS) linearity of 5.8 V, two-terminal off-state gate-drain breakdown voltage (BVGD) of −404 V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 364 V at 300 K are obtained for the present MOS-HFET. The device has demonstrated high spectral responsivity (SR) of 737 A W−1 under 250 nm deep-UV radiation.

Optimization of guard rings construction and epitaxial film resistivity of power <i>n</i>-channel DMOS-transistor

Powerful n-channel DMOS-transistor with drain-source breakdown voltage Uds br value over 800 V and thresh-old voltage from 2 to 5 V was considered in this paper. One or more guard rings are formed on perimeter of such transistor for the breakdown voltage raising. The optimal guard rings construction was described and resistivity value of epitaxial film ρv was determined for obtaining required transistor Uds br value. The regression model was built, with the help of which the most optimal construction variants of guard rings of investigated transistor and resistivity value of epitaxial film, were selected. It was established that the five-dimensional polynomial of second order using as regression model allowed choosing the optimal topological spaces values in the guard rings area and ρv value which made it possible to obtain required Uds br values of the transistor. Experimental values of transistor drain-source breakdown voltage were 876 and 875 V, but calculated values (at identical parameters of definitional regression model) were 874 and 880 V, accordingly, that were errors of 0.23 % and 0.57 %, i. e. made model fits well with experimental data. It was established that ρv makes contribution to breakdown voltages values of the transistor that is more substantial than parameters of guard rings construction. This NDMOS-transistor was manufactured under production conditions of OJSC INTEGRAL” – “INTEGRAL” Holding Managing Company according to the technological route developed by the author. Such device is used in various electronic devices for energetics, in mobile phones, as part of high-voltage integrated circuits of AC/DC- and DC/DC-converters and high-voltage, high-stable LED-drivers.

Al0.75Ga0.25N/AlxGa1-xN/Al0.75Ga0.25N/AlN/SiC Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistors With Symmetrically-Graded Widegap Channel

Novel Al 0.75 Ga 0.25 N/Al x Ga 1-x N/Al 0.75 Ga 0.25 N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with symmetrically-graded widegap Al x Ga 1-x N channel (x = 0.75 → 0.25 → 0.75) grown on a SiC substrate are investigated. Al 2 O 3 was devised as the gate dielectric by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. Device characteristics with respect to different etch depths of the source/drain recesses were studied. For a 2-μm gate length (L G ), the present widegap V-shape-channel MOS-HFET has shown improved maximum drain-source current density (I DS,max ) of 299.3 A/mm at V DS = 20 V, I DS density at V GS = 0 V (I DSS0 ) of 153.9 mA/mm, on/off-current ratio (I on /I off ) of 1.4 × 10 7 , extrinsic transconductance (g m , max ) of 16.7 mS/mm, two-terminal off-state gate-drain breakdown voltage (BV GD ) of -379 V, and three-terminal on-state drain-source breakdown voltage (BV DS ) of 339 V. Besides, superior deep-UV sensing performance with high spectral responsivity (SR) of 1780 (810.2) A/W at wavelength λ = 250 (300) nm are also achieved.

The Effect of Defects with Deep Levels on the C–V Characteristics of High-Power AlGaN/GaN/SiC HEMTs

This study deals with the capacity–voltage (С–V) characteristics of the gate–drain regions of crystals of high-power microwave HEMT transistors with a large gate periphery of the S and Х bands and a source–drain breakdown voltage VDS ranging from 30 to 150 V, as well as test Schottky diodes formed in a single technological cycle together with HEMTs. Capacitance deep-level transient spectroscopy (DLTS) was used to investigate the structural defects creating deep levels. During the investigations, it was shown that the С–V curves of HEMT crystals always had two areas of change in capacitance with differing slope angles, while there were no such knees in the curves for the test Schottky barriers (SBs). The DLTS technique revealed that НЕМТs and test SBs contained electron-like and hole-like traps, occurring, most probably, in the buffer layer, and also a hole-type peak behaving anomalously. The knee in the С–V curves of НЕМТs is due to the strong electric fields arising at the edge of the gate of the transistor structures.

High thermal stability ohmic contacts to nitride semiconductors with refractory metal sidewall diffusion barrier deposited by magnetron sputtering

GaN HEMTs are generally promising candidates for RF and switching power transistors due to their high breakdown strength and the high current density giving a low on-resistance. Low-resistance ohmic contacts are needed to reduce losses and self-heating. Conventional ohmic contacts use Ti and Al with a cap to avoid oxidation of the Al layer. Alternative ohmic metals for use with nitride semiconductors are being sought using Hf or Ta, which can be annealed at lower temperatures. That have been shown, the Au-free low temperature Ta/Al ohmic contacts fabricated with the refractory sidewall diffusion barrier have the lower contact resistance and the better surface morphology after the high temperature annealing. Normally-off p-gate high voltage GaN transistor based on Ta/Al ohmic contacts with the sidewall diffusion barrier have the higher drain-source current, lower gate-source current and higher source-drain breakdown voltage.

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm−1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

Power switching transistors based on gallium nitride epitaxial heterostructures

The results of the development of power switching transistors based on epitaxial gallium nitride heterostructures to create an energy-efficient conversion technique are presented. The developed powerful GaN transistor operates in enrichment mode with unlocking threshold voltage V th = +1.2 V and a maximum drain-source current I ds = 0.15 A/mm at the drain-source voltage V ds = +8 V. The drain-source breakdown voltage in the closed state is V b = 300 V at the drain-source distance L ds = 8.5 μm and drain-source voltage V ds = 0 V.

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO2 charge trapping layer, Al2O3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al2O3/HfO2/Al2O3/Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BVg), source-drain breakdown voltage (BVDS) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications.

Al2O3-Passivated Graded-Barrier AlxGa1-xN/AlN/GaN/Si Heterostructure Field-Effect Transistor by Hydrogen Peroxide Oxidization Method

This letter reports a novel Al2O3-passivated graded-barrier (GB) AlxGa1-xN/AlN/GaN/Si heterostructure field-effect transistor (HFET) formed by using hydrogen peroxide (H2O2) oxidization method. Different from the Al0.26Ga0.74N conventional barrier (CB), a compositionally graded AlxGa1-xN (x = 0.22∼0.3) barrier was devised to increase the Schottky-barrier height (ΦB) and improve the interfacial quality at the same time. Reduced gate leakage and enhanced device gain are further achieved by the Al2O3 passivation. The present Al2O3-passivated/unpassivated GB-HFETs (unpassivated CB-HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 708/699 (654) mA/mm at VDS = 7 V, maximum extrinsic transconductance (gm, max) of 139/126 (113) mS/mm, subthreshold swing (SS) of 176/253 (274) mV/dec, on/off-current ratio (Ion/Ioff) of 3.8 × 106/1.4 × 104 (7.1 × 103), two-terminal off-state gate-drain breakdown voltage (BVGD) of −126.4/−96.8 (−89.3) V, turn-on voltage (Von) of 1.1/0.7 (0.3) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 109/89 (71) V.

Ti0.5Al0.5O-Dielectric AlGaN/GaN/Si Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors by Using Non-Vacuum Ultrasonic Spray Pyrolysis Deposition

This work investigates a Ti0.5Al0.5O-dielectric Al0.26Ga0.74N/GaN metal-oxide-semiconductor heterostructure field-effect transistor (MOS-HFET) grown on a Si substrate, prepared by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. High dielectric constant (k) was characterized to be 29.1 for a 20-nm thick Ti0.5Al0.5O. Hooge coefficient (αH), low-frequency noise spectra (1/f), high/low frequency capacitance-voltage (C-V), pulse I-V measurements were also performed to investigate the improved passivation and insulation of the MOS-structure. The present MOS-HFET design has exhibited superior improvements of 23% in maximum drain-source current density (IDS, max), 25.1% in drain-source saturation current density at VGS = 0 V (IDSS0), 46.3% in two-terminal off-state gate-drain breakdown voltage (BVGD), and 65% in three-terminal drain-source breakdown voltage (BVDS), as compared to a reference Schottky-gate HFET device. Enhanced high-frequency, power, and high-temperature performances up to 450 K are also studied.

101-GHz InAlN/GaN HEMTs on Silicon With High Johnson’s Figure-of-Merit

In this brief, the InAlN/GaN high-electron mobility transistors (HEMTs) on silicon substrate with high Johnson’s figure-of-merit (J-FOM) are presented. A trilayer photoresist of polymethylmethacrylate (PMMA)/copolymer/PMMA associated with a T-shaped gate is used to reduce the parasitic resistance while maintaining high current gain cutoff frequency. The small dc-to-RF transconductance dispersion of only 1.1% suggests a good quality SiN x passivation layer, and the $f_{\rm MAX}$ of 101 GHz and $f_{T}$ of 60 GHz can be simultaneously obtained with a 0.11- $\mu \text{m}$ foot length and 1.5- $\mu \text{m}$ source-drain distance. In addition, the three-terminal OFF-state breakdown measurements reveal a source-drain breakdown voltage (BV $_{\rm DS})$ of 21 V ( $V_{\rm DG}=31$ V). The results lead to a high J-FOM of 1.3 THz $\,\cdot \,\text{V}$ , which has not been reported for the InAlN/GaN HEMTs on silicon substrate.

Improvement of the Current Gain Stability of SiC Junction Transistors

SiC Junction Transistors (SJTs) with 1900 V Drain-Source breakdown voltages, current gain (hFE) higher than 120 and low on-resistance of 22 mΩ (3.5 mΩ-cm2) are reported in this paper. SJTs with a pre-stress hFE of 90 suffer only a 10% reduction of the hFE after 190 hours under a 200 A/cm2 DC current stress at a TJ of 125°C, while a similar stress on earlier generation SJTs resulted in over 25% hFE reduction in only 25 hours. SJT die with pre-stress hFE in the range of 120-125 show absolutely no current gain degradation even after a 300°C/ 2 hour stress at 60 A/cm2 DC drain current.

Dual Ground Plane EDMOS in 28 nm FDSOI for 5 V power management applications

A promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28nm Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB–FDSOI). The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. The idea is to implement two different ground planes under the device to control separately the electrostatic properties of the channel and the drift regions. We show that the separate biasing of the two ground planes enables the independent tuning of the threshold voltage (VTH) as well as the improvement of drain–source breakdown voltage (BV) and specific on-resistance (RON.S). In this work, we explore the electrical characteristics, such as RON.S and BV, as a function of the back-gate voltage and geometry. We report and discuss encouraging results for 5V switched mode applications and power management in ultra-thin SOI technology.

Heterojunction-Free GaN Nanochannel FinFETs With High Performance

Heavily doped GaN nanochannel fin-shaped field-effect transistors (FinFETs) without heterojunction have been fabricated and characterized for the first time. Simplified pragmatical technology for GaN epitaxial growth and FinFET process was used to achieve nanodevices with a channel width from 40 to 100 nm and a gate length of 1 μm. They exhibit excellent on-state performance, such as maximum drain current of 670 mA/mm and maximum transconductance of 168 mS/mm. Record off-state performance was measured: extremely low leakage current of ~ 10-11 mA and source-drain breakdown voltage of ~280 V. The subthreshold slope of 68 mV/decade is close to the theoretical limit (60 mV/decade, so far achieved only in SOI MOSFETs) and leads to very high Ion/Ioff ratio of 108 - 109. The proposed heterojunction-free nanochannel GaN FinFET is a very promising candidate not only for high-performance and high-speed integrated circuits but also for high-power applications.

4H-SiC Trench MOSFET with Thick Bottom Oxide

A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.

(Invited) FinFET Flash Memory Technology

The crystal-Si and poly-Si fin-channel flash memories with a thin n+-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BVDS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.