Source Degeneration Technique Research Articles

Novel low noise amplifier approach for deep brain stimulation

This paper presents an analysis for a multi-stage Low Noise Amplifier (LNA) for application on deep brain stimulation. A low noise amplifier (LNA) with high gain, moderate bandwidth and reduced noise is designed and simulated using LT Spice and PTM BSIM4 CMOS models. The novel LNA circuit topology is proposed which uses a cascaded style to improve mid-band gain of an LNA. The proposed LNA achieves a gain margin which ranges between 60-67 (dB), 2X times; Phase Margin which ranges between 145 to 154 (deg), 3X times; Gain which ranges between 66 to 75 (dB), 2X times and bandwidth from kHz to MHz range. The current biasing circuit is used for enhancing stability and gain range. Also, optimal noise figure is achieved with the help of cascading input matching along with source degeneration technique.

Design and performance analysis of low phase noise LC-voltage controlled oscillator

Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The p ost layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µ m 2 .

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

This study reports a voltage-controlled oscillator (VCO) implemented in a 0.18-μm CMOS process. By utilizing an inductive dual-balance source degeneration (IDSD) technique with a current-reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1- and 10-MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures-of-merits (FOMs) of the proposed VCO at 1- and 10-MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.

Hybrid CMOS-Memristor based operational transconductance amplifier for high frequency applications

This paper deals with designing an optimized hybrid Operational Transconductance Amplifier (OTA) employing a technique called source degeneration with adaptive biasing that can be used for high frequency applications. This work targets implementation of a simple technique with less number of circuit elements which reduces the die area and power consumption and gives rise to good results. The circuit has been designed to operate with a supply voltage of ±1 V along with a bias current. The linearity which is the major drawback of the conventional Complementary Metal Oxide Semiconductor (CMOS) OTA gets improved with source degeneration technique using a non-CMOS non-volatile memory (so-called memristor). The gain-bandwidth product gets improved for an 80pF load. A biquad OTA-C filter is designed and implemented utilizing the OTA designed in this work as an application example. The realization of a high pass filter has been demonstrated. All the simulations were carried out in the Cadence® Virtuoso environment using 180 nm CMOS technology. Another facet of this paper is the memristor compatibility with the CMOS process technology.

Design of 2.4 GHz Improved Current Reuse Gilbert Mixer with Source Degeneration Technique

Design of 2.4 GHz Improved Current Reuse Gilbert Mixer with Source Degeneration Technique

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

Realization of LNA and Mixer Using CMOS 0.18μm Technology for 3.1 to 10.6 GHz

In this paper, low noise amplifier and mixer circuits are realized using 0.18μm CMOS technology in the frequency range of 3.1 to 10.6 GHz. LNA circuit uses the cascade topology with source degeneration technique, which help in reducing the non-linearity in the circuit. The current reuse topology is used to decrease the biasing voltage and hence to decrease the power consumption in the circuit. Realized circuit simulated in 0.18μm technology and various results shows highest gain S21 is 19.982dB and has the positive value in the entire frequency band, minimum NFmin is 1.270dB occurs at 1.27GHz and the highest NFmin is 3.4dB. S11 i.e. input reflection coefficient is -31.670dB and it is negative throughout the entire frequency range while the reflection at output port is report to be -7.449 dB. The resistive feedback topology helps in getting the flat gain in the frequency. Mixer circuit is also realize in 0.18μm CMOS technology, which uses current bleeding topology. Transformer help in converting the single ended signal into differential format. Maximum value of gain is 6.584dB, gain is positive in the entire RF frequency range, S11 i.e. the reflection at port1, which give the negative values in the entire frequency band, simulation of S12 i.e. leakage between the port 1 and 2 has negative values in the entire frequency band means proper isolation between the ports. The future work can the realization of the superheterodyne receiver in UWB band.

A Novel Low-Power Notch-Enhanced Active Filter for Ultrawideband Interferer Rejected LNA

In this article, a novel low-power notch-enhanced active filter is presented using the feedback notch-enhanced (FNE) technique. The active notch filter is proposed based on an area-saving second-order $LC$ series resonator. The passive devices’ loss can be effectively eliminated by the generated dc power-independent negative resistance by inserting a current feedback transistor. Moreover, the capacitive source degeneration (CSD) technique is proposed to boost the filter $Q$ by shifting the series resonant frequency to the negative-resistance region. To demonstrate the feasibility and practicability of the proposed notch filter, a 3.1–10.6-GHz IEEE 802.11a interferer rejected low-noise amplifier (IR-LNA) is fabricated in a 0.13- $\mu {\hbox {m}}$ CMOS process. The multistage structure, consisting of a common-gate (CG) stage with a dual-resonance load and a cascode stage with the proposed active notch filter, is employed for wideband input matching, gain flatness, and interferer rejection (IR) simultaneously. The measurements show that the IR-LNA provides a maximum of 16.05-dB power gain, 2.08–3.70-dB noise figure (NF) in the desired band, and a maximum of 40.9-dB IR ratio (IRR) at 5.77 GHz, with a power consumption of 10.2 mW, while the active notch filter only consumes 456- $\mu {\hbox {A}}$ current.

A high linearity high speed time-interleaved track and hold circuit

This paper presents a high linearity 4GS/s 4-way time-interleaved track and hold circuit in 65nm CMOS process. A high linearity track and hold amplifier is designed for each single channel, which utilizes open-loop structure instead of traditional closed-loop structure used in low speed applications. In the presented design, we introduced clock-boosting switches and buffers applying source degeneration technique to enable the high linearity. Meanwhile signal feedthrough is cancelled by dummy switches. The proposed design finally achieves over 52 dB signal to noise and distortion ratio (SNDR) for a 400 mV input Vpp at 4GS/s sampling rate.

Three‐bit 2–18 GHz all‐pass network‐based trombone phase delay line with improved insertion loss variation

A complementary metal–oxide–semiconductor (CMOS) trombone true-time delay (TTD) operating from 2 to 18 GHz is presented. The second-order all-pass network (APN) is used to construct the delay lines. The higher-order delay response of the APN allows for a better trade-off between the delay and bandwidth compared to the artificial transmission line structures. The all-pass characteristic of the APN further improves the matching performance of the TTD. In order to improve the insertion loss (IL) variations between different delay states, the source degeneration by resistor–capacitor structure is used for the switching amplifiers. Two 3-bit TTDs are fabricated in a standard 0.13 µm CMOS process, namely TTD 1 and TTD 2. TTD 1 is based on conventional switching amplifiers and TTD 2 adopts the proposed source degeneration technique. The measurement results show that the root-mean-square IL variation of TTD 1 and TTD 2 is better than 2 and 1.4 dB. The input and output return loss of the two TTDs is >12 dB. Delays of 270 and 265 ps are achieved by TTD 1 and TTD 2. The power consumption for TTD 1 is 2–6.2 mW and is 2–3.6 mW for TTD 2.

A Sub-2 dB NF, 0.3–3 GHz Packaged Bandwidth Extended Wideband Receiver Front-End

This brief presents a sub-2 dB noise figure (NF) packaged wideband receiver front-end for high sensitivity multi-standard radio. An inductive source degeneration technique with a low- $V_{T}$ CMOS transistor is adopted in composite pair low noise amplifier (CPLNA) to extend the bandwidth and to improve the NF, a current commutating multi-gate transistor pair (MGTR) down conversion passive mixer for better linearity of the packaged receiver. Fabricated in 65 nm CMOS technology, the receiver provides a maximum conversion voltage gain of 37 dB and NF of 1.85–2 dB with a 3 dB bandwidth from 0.3 GHz to 3 GHz in quad-flat no-leads (QFN) package. The receiver has a third-order intermodulation intercept point (IIP3) of −7 dBm at 2 GHz and consumes a 44.5 mW power (LNA + Mixer).

Design of high-linearity 75–90 GHz CMOS down-conversion mixer for automotive radar

This paper presents a 75–90 GHz down-conversion mixer applied in automotive radar, which is characterized with high linearity, low local oscillator (LO) drive as well as high conversion gain (CG) using TSMC 65-nm CMOS general-purpose technology. The good linearity and isolation of mixer are required for automotive radar to cover short-middle-far range detection. The mixer includes an enhanced double-balanced Gilbert-cell core with series peaking transmission line and source degeneration technique for improving linearity and CG, two on-chip baluns and intermediate frequency (IF) buffer for IF test. Besides, to make the design more accurate and efficient, the modeling and design of millimeter-wave (mm-wave) passive devices are introduced. The mixer consumes 12 mW under 1.5 V. The input 1 dB compression point (P1dB) is 2.5 dBm as well as IIP3 of 13.2 dBm at 80 GHz. High performances are achieved with the CG of 5 dB at 76 GHz with LO power of 0 dBm for frequencies of 75–90 GHz which covers the application of automotive radar frequency band (76–81 GHz) and LO-RF isolation of 33–37 dB for frequencies of 60–90 GHz. The area of the mixer is 0.14 mm2, with PADs included.

Low Voltage Low Power Single Ended Operational Transconductance Amplifier for Low Frequency Applications

This paper presents the designing of a low voltage low power single ended operational transconductance amplifier (OTA) for low frequency application. The designed OTA combines three different schemes i.e. current splitting, current cancellation and source degeneration technique. Source degeneration method using resistor is one of the most simple and ubiquitous technique to linearize the transfer characteristics of OTA. Current splitting technique is utilized to reduce the transconductance of OTA and to improve the linearity. Current cancellation technique is used to further reduce the transconductance. The OTA circuit is operated in sub-threshold region due to the stringent power limitation requirement in integrated circuits. The transconductance of the OTA is 4.5 nA/V with a linear range of +/− 0.25 V. To test the applicability of the proposed OTA, a fifth order Butterworth OTA-C low pass filter is realized. The circuit is operated at a supply voltage of +/− 0.5 V and the power consumption of the filter is 487 nW. The DC gain of the filter is − 6.1 dB with a cutoff frequency of 250 Hz. THD of − 50.61 dB of the OTA-C filter is obtained for a 100 mVpp signal with 100 Hz frequency. The circuit shows the best THD performance with less pass band attenuation for single ended filter circuit. The circuit is simulated in cadence environment using 150 nm CMOS process technology.

Adjustably transconductance enhanced bulk‐driven OTA with the CMOS technologies scaling

An adjustably transconductance enhanced bulk-driven operational transconductance amplifier (OTA) working at weak inversion region is presented. Based on the traditional positive feedback source degeneration technique, a proposed current-shunt auxiliary amplifier is employed here to modulate the gate of input differential pairs, achieving a further improvement of the effective transconductance with the CMOS technologies scaling. In addition, an adjustable transconductance enhancement factor is obtained, leading to an enhanced stability performance. Both conventional and proposed bulk-driven OTAs are designed and simulated on CSMC 180 nm process. The simulated results demonstrate that the unity gain-bandwidth of the proposed bulk-driven OTA is improved by 120% compared to that of the conventional counterpart with a little neglected increased power consumption.

77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

AbstractThe design and implementation of a 77 GHz phase‐locked loop (PLL) for automobile radar system in 90 nm CMOS technology is demonstrated. To enhance the operation frequency range of the voltage‐controlled oscillator in the PLL, reversely tunable LC source degeneration technique is adopted. To improve the frequency locking range of the divide‐by‐3 injection‐locked frequency divider in the PLL, a parallel inductor is used to parallel resonate the parasitic capacitance of the cross‐coupled transistors. In addition, a phase and frequency detector with enhanced D flip flops is used to effectively reduce the dead zone. The PLL consumes only 49.6 mW and exhibits an operation range of 2.4 GHz (76.8∼79.2 GHz) and reference sidebands of <–56 dBc. The chip area of the PLL is only 0.656 mm2 excluding the test pads.

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9V shows a high DC gain of 63dB with a unity gain frequency at 3.5MHz, a wide dynamic range and a total harmonic distortion of −60dB at 1MHz for an input of 1Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56MHz and voltage mode of 16.78MHz cut-off frequency f-3dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18μm TS18SL.

Linearity enhancement in the entire tuning range of CMOS OTA using a new tune compensated source degeneration technique

This paper presents a tunable linear OTA based on an improved adaptive biasing of degeneration triode-mode transistor and a new technique for compensating the linearity degradation due to the tuning action. Using the adaptive biasing circuit, the degeneration resistance is modulated such that to make constant transconductance in a wide range of input voltages. As the linearity would be lost at higher values of transconductance, a tune-dependent current is injected to the adaptive biasing circuit to remove the nonlinearities of OTA's second stage. Using 1.8V supply voltage, the proposed OTA consumes 600μW in which the portion of adaptive biasing and the tune compensation circuits is 37μW. When a 0.9 Vp-p, 10MHz input voltage is applied to the OTA which is tuned at highest Gm, HD3 decrement due to using adaptive biasing circuit is 3.7dB, while it reduces to 11.3dB due to using both adaptive biasing and tune compensation circuits.

CMOS transconductor with improved linearity using the bulk of self‐cascode transistors

A novel transconductor based on the source degeneration technique is introduced. The proposed solution includes self-cascode transistors as input devices, additionally employing their bulk terminal to increase the linearity. Input transconductance characteristics are improved as compared with conventional topologies without considerably increasing power consumption and die area. The circuit was designed and fabricated in a standard 0.18 μm CMOS technology to operate with a 1.8 V single supply voltage. Experimental results showed a linearity improvement of 20 dB for an input signal of 0.2 V at 100 kHz.

A Novel Design of Low-Voltage VDIBA and Filter Application

In this study, a low-voltage low-power design of previously introduced analog signal processing element called as Voltage Differencing Inverting Buffered Amplifier (VDIBA) is presented. Level shifter current mirrors are used in the circuit design in order to accomplish the low-voltage low-power operation. The configuration operates only with ±0.4 V supply voltages and consumes power 569 µW at the bias current 50 µA. Also, low-voltage transconductor which has highly linear g m is executed with the use of bulk-driven quasi-floating gate (BD-QFG) and source degeneration techniques. The simulations of the introduced circuit have been performed with 0.18 μm TSMC CMOS technology by SPICE. The theoretical approaches have been confirmed by the simulation results. DOI: http://dx.doi.org/10.5755/j01.eie.22.6.17224

Low Noise Low Power CMOS Telescopic-OTA for Bio-Medical Applications

The preamplifier block is crucial in bio-medical signal processing. The power intensive Operational Transconductance Amplifier (OTA) is considered, and the performance of preamplifier is studied. A low noise and low power telescopic OTA is proposed in this work. To reduce the noise contribution in the active load transistors, source degeneration technique is incorporated in the current stealing branch of the OTA. The OTA design optimization is achieved by g m / I d methodology, which helps to determine the device geometrical parameters (W/L ratio). The proposed design was implemented in CMOS 90 nm with bias current and supply voltage of 1.6 µA and 1.2 V, respectively. The post layout simulation results of the proposed amplifier gave a gain of 62 dB with phase margin 57°, CMRR 78 dB, input referred noise 3.2 µVrms, Noise Efficiency Factor (NEF) 1.86 and power consumption of 1.92 µW.