A high linearity high speed time-interleaved track and hold circuit

Abstract

This paper presents a high linearity 4GS/s 4-way time-interleaved track and hold circuit in 65nm CMOS process. A high linearity track and hold amplifier is designed for each single channel, which utilizes open-loop structure instead of traditional closed-loop structure used in low speed applications. In the presented design, we introduced clock-boosting switches and buffers applying source degeneration technique to enable the high linearity. Meanwhile signal feedthrough is cancelled by dummy switches. The proposed design finally achieves over 52 dB signal to noise and distortion ratio (SNDR) for a 400 mV input Vpp at 4GS/s sampling rate.