CMOS transconductor with improved linearity using the bulk of self‐cascode transistors

Abstract

A novel transconductor based on the source degeneration technique is introduced. The proposed solution includes self-cascode transistors as input devices, additionally employing their bulk terminal to increase the linearity. Input transconductance characteristics are improved as compared with conventional topologies without considerably increasing power consumption and die area. The circuit was designed and fabricated in a standard 0.18 μm CMOS technology to operate with a 1.8 V single supply voltage. Experimental results showed a linearity improvement of 20 dB for an input signal of 0.2 V at 100 kHz.