Comparison Of Networks Research Articles

RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm

This paper proposes a novel hardware-based multidimensional sorting algorithm and its respective architecture, called real-time hardware sorter (RTHS), for emerging data intensive processing applications where performance and resource conservation are serious concerns. The basic idea behind RTHS is to reduce the hardware complexity of parallel hardware sorting architectures (PHSAs) through a high-performance scalable matrix-based sorting method. The proposed method can also be used for implementing Min/Max queues or finding the largest/smallest records exclusively in the big data application. Implementing the RTHS design on a Virtex-7 field-programmable gate array (FPGA) reveals that the number of lookup tables (LUTs) of the proposed method has decreased by 66.3% and 87.3% compared to the conventional Bitonic sorting network (CBSN) and the state-of-the-art PHSA, respectively. In addition, the number of required registers for the proposed method has decreased by 94.8% compared to the state-of-the-art PHSA.

A Modified Inexact Arithmetic Median Filter for Removing Salt-and-Pepper Noise From Gray-Level Images

We have recently proposed approximate median filters (APMFs). They are based on the sorting network and achieve acceptable image quality under low-cost hardware. In this brief, we develop a specific comparator to improve the capabilities of those filters in noise elimination. The architecture of our inexact median filters (IMFs) is regular and modular. Also, we introduce the histogram-based error dispersion plot as a new error evaluation method to have a better assessment of IMF performance. Simulation results show that the proposed filter is effectively low cost in power, area, and speed. Despite the tradeoff between the filtering accuracy and circuit characteristics, the output quality of the filter is largely similar to that of the precise one. Also, the degradation is almost not noticeable to the human eye.

Evolutionary Development of Growing Generic Sorting Networks by Means of Rewriting Systems

This paper presents an evolutionary developmental method for the design of arbitrarily growing sorting networks. The developmental model is based on a parallel rewriting system (a grammar) that is specified by an alphabet, an initial string (an axiom), and a set of rewriting rules. The rewriting process iteratively expands the axiom in order to develop more complex strings during a series of development steps (i.e., derivations in the grammar). A mapping function is introduced that allows for converting the strings onto comparator structures—building blocks of sorting networks. The construction of the networks is performed in such a way that a given (initial) sorting network grows progressively by adding further building blocks within each development step. For a given (fixed) alphabet, the axiom together with the rewriting rules themselves are the subjects of the evolutionary search. It will be shown that suitable grammars can be evolved for the construction of arbitrarily large sorting networks that grow with various given sizes of development steps. Moreover, the resulting networks exhibit significantly better properties (the number of comparators and delay) in comparison with those obtained by means of similar existing methods.

Encoding cardinality constraints using multiway merge selection networks

Boolean cardinality constraints (CCs) state that at most (at least, or exactly) k out of n propositional literals can be true. We propose a new, arc-consistent, easy to implement and efficient encoding of CCs based on a new class of selection networks. Several comparator networks have been recently proposed for encoding CCs and experiments have proved their efficiency (Abío et al. 2013, Asín et al. Constraints 12(2): 195–221, 2011, Codish and Zazon-Ivry 2010, Eén and Sörensson Boolean Modeling and Computation 2: 1–26, 2006). In our construction we use the idea of the multiway merge sorting networks by Lee and Batcher (1995) that generalizes the technique of odd-even sorting ones by merging simultaneously more than two subsequences. The new selection network merges 4 subsequences in that way. Based on this construction, we can encode more efficiently comparators in the combine phase of the network: instead of encoding each comparator separately by 3 clauses and 2 additional variables, we propose an encoding scheme that requires 5 clauses and 2 variables on average for each pair of comparators. We also extend the model of comparator networks so that the basic components are not only comparators (2-sorters) but more general m-sorters, for m ∈ {2, 3, 4}, that can also be encoded efficiently. We show that with small overhead (regarding implementation complexity) we can achieve a significant improvement in SAT-solver runtime for many test cases. We prove that the new encoding is competitive to the other state-of-the-art encodings.

Model-Predictive-Control-Based Capacitor Voltage Balancing Strategies for Modular Multilevel Converters

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms.

The local limit of random sorting networks

A sorting network is a geodesic path from $12 \cdots n$ to $n \cdots 21$ in the Cayley graph of $S_n$ generated by adjacent transpositions. For a uniformly random sorting network, we establish the existence of a local limit of the process of space-time locations of transpositions in a neighbourhood of $an$ for $a\in[0,1]$ as $n\to\infty$. Here time is scaled by a factor of $1/n$ and space is not scaled. The limit is a swap process $U$ on $\mathbb{Z}$. We show that $U$ is stationary and mixing with respect to the spatial shift and has time-stationary increments. Moreover, the only dependence on $a$ is through time scaling by a factor of $\sqrt{a(1-a)}$. To establish the existence of $U$, we find a local limit for staircase-shaped Young tableaux. These Young tableaux are related to sorting networks through a bijection of Edelman and Greene.

Greedy Best-First Search for the Optimal-Size Sorting Network Problem

In this paper we present an effective algorithm for creating minimal-size sorting networks. Our approach is based on incrementally constructing sets of sorting networks, starting from a specified prefix and adding gradually new comparators. At each step, in order to limit the size of these sets, only the most promising candidates are considered. We introduce a novel rule for implementing the selection of candidates, based on analyzing the structure of a network’s output, instead of simply considering its size. For 16 wires, the running time necessary to determine a sorting network was reduced up to 90 times, compared to state-of-the-art results [21].

ОБЧИСЛЮВАЛЬНА СКЛАДНІСТЬ МЕРЕЖЕВОЇ МОДЕЛІ СОРТУВАННЯ ЛІНІЙНОГО МАСИВУ ЧИСЕЛ

In the development of advanced software and hardware for modern computing, the interest is the improvement of methods of associative processing of information such as procedures of sorting and selection. That ensures the realization of effective search for the required information in the data arrays. The need for parallel non-processing of large amounts of information entails the appropriate organization of associative memory, as well as the development and using of perspective technical devices. The sorting is important procedure in such application areas as solving economic problems, managing databases, sorting of IP addresses in computer networks, processing signals and images (for example, in nonlinear median image filtering). The analysis of known sorting methods have shown that the most effective method of parallel sorting, taking into account its hardware implementation by the sorting network, is the pairwise exchange. At the same time, the degree of parallelism of any sorting method for its hardware implementation directly depends on the number of comparison schemes that work in parallel in each view. For a pairwise exchange method, the degree of parallelism is determined by the value ]n/2[, where n is the number of input numerical values ​​or the dimension of the input linear number array. In this article methods of implementing of the sorting algorithm by the method of pairwise exchange with the link topology between elements of the number array in the form of tape and ring are analyzed. For example, the parallel sorting algorithm using the pairwise exchange method is described. The simulation at a high-level C ++ language is done. The obtained statistical and graphic results of modeling are analyzed. The analysis of graphical modeling results shows the dependence of the form O(n) between the number of sort cycles and the dimensionality n of the input array. That confirms the effectiveness of the hardware implementation of sorting by pairwise exchange on the sorting network due to the regularity of the structure and connections in the sorting process. The ability to statistically determine not only the number of sorting cycles with a given dimension of the number array, but also the corresponding number of comparisons and transposition greatly extends the possibilities of improving the known and creating new ways of synchronous sorting of elements of a linear array by hardware in the form of a sorting network.

Power optimized Hybrid Sorting based Median Filtering

Nowadays, embedded video and image processing capabilities are much more demands with image quality. Digital image noise mostly occurs in a communication channel. The variety of random variation of white and black dots on the surface of an image, seriously degrading the image quality. Median filters are having the excellent image denoising processing capabilities. These filters are particularly reducing the salt-and-pepper noise and increase the throughput with less complexity. In contrast, power efficient remains an untapped area for improvement in the sorting-based network. For this, the filter is designed with hybrid sorting network with intelligent clock gating technique is also presented. The implementation of median filter on ARTIX-7 (90 nm) FPGA. The practical results shows the effectiveness of combined parallel and pipelined with clock gating architecture reduces the dynamic power and complexities in terms of FPGA resource usage and frequency.

BulkSort: System Design and Parallel Hardware Implementation Considerations

Algorithms are commonly perceived as difficult subjects. Many applications today require complex algorithms. However, the researchers look for ways to make them as simple as possible. In high time demanding fields, the process of sorting represents one of the foremost issues in the data structure for searching and optimization algorithms. In parallel processing, we divide program instructions among multiple processors by breaking problems into modules that can be executed in parallel, to reduce the execution time. In this paper, we proposed a novel parallel, re-configurable and adaptive sorting network of the BulkSort algorithm. Our architecture is based on simple and elementary operations such as comparison and binary shifting. The main strength of the proposed solution is the ability to sort in parallel without memory usage. Experimental results show that our proposed model is promising according to the required resources and its ability to perform a high-speed sorting process. In this study, we take into account the analysis result of the Simulink design to establish the required hardware resources of the proposed system.

Random sorting networks: local statistics via random matrix laws

This paper finds the bulk local limit of the swap process of uniformly random sorting networks. The limit object is defined through a deterministic procedure, a local version of the Edelman-Greene algorithm, applied to a two dimensional determinantal point process with explicit kernel. The latter describes the asymptotic joint law near $0$ of the eigenvalues of the corners in the antisymmetric Gaussian Unitary Ensemble. In particular, the limiting law of the first time a given swap appears in a random sorting network is identified with the limiting distribution of the closest to $0$ eigenvalue in the antisymmetric GUE. Moreover, the asymptotic gap, in the bulk, between appearances of a given swap is the Gaudin-Mehta law -- the limiting universal distribution for gaps between eigenvalues of real symmetric random matrices. The proofs rely on the determinantal structure and a double contour integral representation for the kernel of random Poissonized Young tableaux of arbitrary shape.

Design space exploration of multi-core RTL via high level synthesis from OpenCL models

As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of available computing power. Designing optimized accelerators that can meet particular requirements has always presented a tremendous challenge to hardware engineers. To do so, designers have to trade off performance for power consumption in a manner such that the final RTL consumes minimum energy to meet the required performance (e.g. FLOPS) target. Moreover, the growing trend towards heterogeneous platforms is crucial to meet time and power consumption constraints of high-performance computing (HPC) applications. The OpenCL parallel programming language and framework enables programming CPU, GPU and recently FPGAs using the high-level synthesis (HLS) methodology. This work presents a design space exploration flow based on execution time, resource utilization and power consumption of OpenCL kernels mapped on FPGAs using the Xilinx high-level synthesis tool chain. Our experiments suggest that the quality of generated solutions, in terms of performance-per-watt, can be determined using analytical formulas prior to implementation, thus enabling fast and accurate DSE by considering on-chip and off-chip sources of parallelism. Moreover, the automated flow suggests design hints to meet a given time constraint within available resources. The proposed technique is demonstrated by optimizing the well known bitonic sorting network from NVIDIA’s OpenCL benchmark. Our results report that FPGAs have at least 20% higher performance-per-watt with respect to two high-end GPUs manufactured in the same technology (28 nm). Additionally, FPGAs with more available resources and using a more modern process (20 nm) can outperform the tested GPUs while consuming at least 55% less power at the cost of more expensive devices.

FPGA-Based Implementation of MMC Control Based on Sorting Networks

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.

A Web Page Clustering Method Based on Formal Concept Analysis

Web page clustering is an important technology for sorting network resources. By extraction and clustering based on the similarity of the Web page, a large amount of information on a Web page can be organized effectively. In this paper, after describing the extraction of Web feature words, calculation methods for the weighting of feature words are studied deeply. Taking Web pages as objects and Web feature words as attributes, a formal context is constructed for using formal concept analysis. An algorithm for constructing a concept lattice based on cross data links was proposed and was successfully applied. This method can be used to cluster the Web pages using the concept lattice hierarchy. Experimental results indicate that the proposed algorithm is better than previous competitors with regard to time consumption and the clustering effect.

Identifying feasible operating regimes for early T-cell recognition: The speed, energy, accuracy trade-off in kinetic proofreading and adaptive sorting.

In the immune system, T cells can quickly discriminate between foreign and self ligands with high accuracy. There is evidence that T-cells achieve this remarkable performance utilizing a network architecture based on a generalization of kinetic proofreading (KPR). KPR-based mechanisms actively consume energy to increase the specificity beyond what is possible in equilibrium. An important theoretical question that arises is to understand the trade-offs and fundamental limits on accuracy, speed, and dissipation (energy consumption) in KPR and its generalization. Here, we revisit this question through numerical simulations where we simultaneously measure the speed, accuracy, and energy consumption of the KPR and adaptive sorting networks for different parameter choices. Our simulations highlight the existence of a “feasible operating regime” in the speed-energy-accuracy plane where T-cells can quickly differentiate between foreign and self ligands at reasonable energy expenditure. We give general arguments for why we expect this feasible operating regime to be a generic property of all KPR-based biochemical networks and discuss implications for our understanding of the T cell receptor circuit.

Low-Cost Sorting Network Circuits Using Unary Processing

Sorting is a common task in a wide range of applications from signal and image processing to switching systems. For applications that require high performance, sorting is often performed in hardware with application-specified integrated circuits or field-programmable gate arrays. Hardware cost and power consumption are the dominant concerns. The usual approach is to wire up a network of compare-and-swap units in a configuration called the Batcher (or bitonic) network. Such networks can readily be pipelined. This paper proposes a novel area-efficient and power-efficient approach to sorting networks, based on “unary processing.” In unary processing, numbers are encoded uniformly by a sequence of one value (say 1) followed by a sequence of the other value (say 0) in a stream of 0’s and 1’s with the value defined by the fraction of 1’s in the stream. Synthesis results of complete sorting networks show up to 92% area and power saving compared to the conventional binary implementations. However, the latency increases. To mitigate the increased latency, this paper uses a novel time-encoding of data. The approach is validated with two implementations of an important application of sorting: median filtering. The result is a low cost, energy-efficient implementation of median filtering with only a slight accuracy loss, compared to conventional implementations.

Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences

Stochastic computing (SC) often requires long stochastic sequences and, thus, a long latency to achieve accurate computation. The long latency leads to an inferior performance and low energy efficiency compared with most conventional binary designs. In this paper, a type of low-discrepancy sequences, the Sobol sequence, is considered for use in SC. Compared to the use of pseudorandom sequences generated by linear feedback shift registers (LFSRs), the use of Sobol sequences improves the accuracy of stochastic computation with a reduced sequence length. The inherent feature in Sobol sequence generators enables the parallel implementation of random number generators with an improved performance and hardware efficiency. In particular, the underlying theory is formulated and circuit design is proposed for an arbitrary level of parallelization in a power of 2. In addition, different strategies are implemented for parallelizing combinational and sequential stochastic circuits. The hardware efficiency of the parallel stochastic circuits is measured by energy per operation (EPO), throughput per area (TPA), and runtime. At a similar accuracy, the $8{\times}$ parallel stochastic circuits using Sobol sequences consume approximately 1% of the EPO of the conventional LFSR-based nonparallelized circuits. Meanwhile, an average of 70 (up to 89) times improvements in TPA and less than 1% runtime are achieved. A sorting network is implemented for a median filter (MF) as an application. For a similar image processing quality, a higher energy efficiency is obtained for an $8{\times}$ parallelized stochastic MF compared with its binary counterpart.

A Framework for the Automatic Vectorization of Parallel Sort on x86-Based Processors

The continued growth in the width of vector registers and the evolving library of intrinsics on the modern x86 processors make manual optimizations for data-level parallelism tedious and error-prone. In this paper, we focus on parallel sorting, a building block for many higher-level applications, and propose a framework for the Automatic SIMDization of Parallel Sorting (ASPaS) on x86-based multi- and many-core processors. That is, ASPaS takes any sorting network and a given instruction set architecture (ISA) as inputs and automatically generates vector code for that sorting network. After formalizing the sort function as a sequence of comparators and the transpose and merge functions as sequences of vector-matrix multiplications, ASPaS can map these functions to operations from a selected “pattern pool” that is based on the characteristics of parallel sorting, and then generate the vector code with the real ISA intrinsics. The performance evaluation on the Intel Ivy Bridge and Haswell CPUs, and Knights Corner MIC illustrates that automatically generated sorting codes from ASPaS can outperform the widely used sorting tools, achieving up to 5.2x speedup over the single-threaded implementations from STL and Boost and up to 6.7x speedup over the multi-threaded parallel sort from Intel TBB.

The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks

In general, efficient non-blocking interconnection networks can be derived from sorting networks, and to this end, one may either follow the merge-based or the radix-based sorting paradigm. Both paradigms require special modifications to handle partial permutations. In this article, we present a general lemma about half cleaner modules that were introduced as building blocks in Batcher’s bitonic sorting network. This lemma is the key to prove the correctness of many known optimizations of interconnection networks. In particular, we first show how to use any ternary sorter and a half cleaner for implementing an efficient split module as required for radix-based sorting networks for partial permutations. Second, our lemma formally proves the correctness of another known optimization of the Batcher-Banyan network.

On the usage of sorting networks to control greenhouse climatic factors

The goal of this article is the application of a non-adaptive classification algorithm to support the variable management process for internal climate control. The protected agriculture has given many advantages for the care and improvement in the production of almost any food. This work is focused on improving a control system for climate variables. The decision for activating an actuator for the correct care of the crop is very important. A sorting network technique with predefined compare–interchange operations and designed to order data very efficiently is proposed. This approach has been applied to the process of handling actuators within a control system. An advantage of using the sorting networks is that it has an inflexibility when processing a data list; it always takes the same units of time and is executed in the same number of operations for an input size of n. Sorting network–based applications are scarce in the state-of-the-art because there are not many techniques that are effective for sorting very small data sizes. The use of sorting networks in the process of assessing the determination of actuators is proposed. This operation is scheduled in the design of control and performed at each reading back data.