Comparison Of Networks Research Articles

Hardware Implementation for Belief Propagation Flip Decoding of Polar Codes

Belief propagation (BP) decoding has natural advantages in throughput for polar codes to meet high-speed and low-latency requirements. The soft outputs of BP decoding can be utilized further for joint detection and decoding in the baseband communication system. However, its error-correction performance is not comparable with the successive cancellation list (SCL) decoding. Belief propagation flip (BPF) decoding is recently proposed to improve the error-correction performance of BP decoding and indicates the potential to compete with SCL decoding. In this paper, we propose an advanced BPF (A-BPF) scheme that reduces the decoding latency with the help of one critical bit and improves the error-correction performance by the proposed joint detection criterion. To improve area efficiency in the hardware level, an optimized sorting network is proposed and applied for the A-BPF decoder. The decoder is implemented on 65 nm CMOS technology for length-1024 and rate-1/2 polar codes, and the results show that the proposed decoder can achieve a close frame error rate performance to the SCL decoder with four lists and deliver a throughput of 5.17 Gb/s at $E_{b}/N_{0}=4.0$ dB.

Secure training of decision trees with continuous attributes

Abstract We apply multiparty computation (MPC) techniques to show, given a database that is secret-shared among multiple mutually distrustful parties, how the parties may obliviously construct a decision tree based on the secret data. We consider data with continuous attributes (i.e., coming from a large domain), and develop a secure version of a learning algorithm similar to the C4.5 or CART algorithms. Previous MPC-based work only focused on decision tree learning with discrete attributes (De Hoogh et al. 2014). Our starting point is to apply an existing generic MPC protocol to a standard decision tree learning algorithm, which we then optimize in several ways. We exploit the fact that even if we allow the data to have continuous values, which a priori might require fixed or floating point representations, the output of the tree learning algorithm only depends on the relative ordering of the data. By obliviously sorting the data we reduce the number of comparisons needed per node to O(N log2 N) from the naive O(N 2), where N is the number of training records in the dataset, thus making the algorithm feasible for larger datasets. This does however introduce a problem when duplicate values occur in the dataset, but we manage to overcome this problem with a relatively cheap subprotocol. We show a procedure to convert a sorting network into a permutation network of smaller complexity, resulting in a round complexity of O(log N) per layer in the tree. We implement our algorithm in the MP-SPDZ framework and benchmark our implementation for both passive and active three-party computation using arithmetic modulo 264. We apply our implementation to a large scale medical dataset of ≈ 290 000 rows using random forests, and thus demonstrate practical feasibility of using MPC for privacy-preserving machine learning based on decision trees for large datasets.

Engineering faster sorters for small sets of items

AbstractSorting a set of items is a task that can be useful by itself or as a building block for more complex operations. That is why a lot of effort has been put into finding sorting algorithms that sort large sets as efficiently as possible. But the more sophisticated and complex the algorithms become, the less efficient they are for small sets of items due to large constant factors. A relatively simple sorting algorithm that is often used as a base case sorter is insertion sort, because it has small code size and small constant factors influencing its execution time. We aim to determine if there is a faster way to sort small sets of items to provide an efficient base case sorter. We looked at sorting networks, at how they can improve the speed of sorting few elements, and how to implement them in an efficient manner using conditional moves. Since sorting networks need to be implemented explicitly for each set size, providing networks for larger sizes becomes less efficient due to increased code sizes. To also enable the sorting of slightly larger base cases, we adapted sample sort to Register Sample Sort, to break down those larger sets into sizes that can in turn be sorted by sorting networks. From our experiments we found that when sorting only small sets of integers, the sorting networks outperform insertion sort by a factor of at least 1.76 for any array size between six and 16, and by a factor of 2.72 on average across all machines and array sizes. When integrating sorting networks as a base case sorter into Quicksort, we achieved far less performance improvements over using insertion sort, which is probably due to the networks having a larger code size and cluttering the L1 instruction cache. The same effect occurs when including Register Sample Sort as a base case sorter for IPSo. But for x86 machines that have a larger L1 instruction cache of 64 KiB or more, we obtained speedups of 12.7% when using sorting networks as a base case sorter in std::sort, and of 5%–6% when integrating Register Sample Sort as a base case sorter into IPSo, each in comparison to using insertion sort as the base case sorter. In conclusion, the desired improvement in speed could only be achieved under special circumstances, but the results clearly show the potential of using conditional moves in the field of sorting algorithms.

Federated Data Cleaning: Collaborative and Privacy-Preserving Data Cleaning for Edge Intelligence

As an important driving factor of emerging Internet-of-Things (IoT) applications, machine learning algorithms are currently facing the challenge of how to “clean” data noise, that is introduced during the training process (e.g., asynchronous execution and lossy data compression and quantization). In an attempt to guarantee data quality, various data cleaning approaches have been proposed to filter out abnormal data entries based on the global data distribution. However, most existing data cleaning approaches are based on a centralized paradigm and thus cannot be applied to future edge-based IoT applications, where each edge node (EN) has only a limited view of the global data distribution. Moreover, the increasing demand for privacy preservation largely prevents ENs from combining their data for centralized cleaning. In this study, we propose a federated data cleaning protocol, coined as FedClean, for edge intelligence (EI) scenarios that is designed to achieve data cleaning without compromising data privacy. More specifically, different ENs first generate Boolean shares of their data and distribute them to two noncolluding servers. These two servers then run the FedClean protocol to privately and efficiently compute the attribute value frequency (AVF) scores of the collected data entries, which are then sorted in ascending order via a bitonic sorting network without revealing their values. As a result, data entries with lower AVF scores are considered as abnormal and filtered out. The security, efficiency, and effectiveness of the proposed approach are then demonstrated via concrete security analysis and comprehensive experiments.

A novel detection fusion network for solid waste sorting

Vision-based object detection technology plays a very important role in the field of computer vision. It is widely used in many machine vision applications. However, in the specific application scenarios, like a solid waste sorting system, it is very difficult to obtain good accuracy due to the color information of objects that is badly damaged. In this work, we propose a novel multimodal convolutional neural network method for RGB-D solid waste object detection. The depth information is introduced as the new modal to improve the object detection performance. Our method fuses two individual features in multiple scales, which forms an end-to-end network. We evaluate our method on the self-constructed solid waste data set. In comparison with single modal detection and other popular cross modal fusion neural networks, our method achieves remarkable results with high validity, reliability, and real-time detection speed.

A robot system equipped with deep convolutional neural network for autonomous grading and sorting of root-trimmed garlics

The demand for smart automation systems in postharvest technology, particularly in the postharvest process of garlic production, is high. In this study, we introduce an artificial intelligence (AI)-integrated robot system for grading and sorting of garlics after root trimming. We developed a robot system that automatically grades and sorts root-trimmed garlics based on image analysis using a deep learning model, which is equipped with a deep convolutional neural network (CNN). The robot system consists of three main modules: image acquisition module (IAM), image processing module (IPM), and garlic sorting module (GSM). The IAM captures a live video of garlic roots using an independent light-emitting diode (LED) and a web camera connected to a computer. The IPM consists of garlic image processing software (GIPS) installed on a Windows 10 computer. GIPS imports videos, detects the shape of garlic bulbs, and predicts the garlic class using the deep learning model. When a garlic bulb shape is detected, the image is preprocessed, and the deep learning model is automatically activated to predict the garlic class. The GSM physically separates garlics into three containers for good, bad, and scratched classes based on a previous predicted result. A total of 800 root-trimmed garlics were tested and evaluated in nine experiments. The processing time to predict classes from a garlic image on a regular laptop computer (Intel® core™ i7-8650U 1.9 GHz CPU, with 16 Gb RAM) was 0.19–0.58 s. The median time to trim and sort one garlic was 11 s (in a setting with three prediction replications), and the overall grading accuracy for the three classes was 89%. The individual predicted precision for the good, bad, and scratched classes was 95%, 68%, and 100%, respectively. Given that the robot system was robust and inexpensive, it has the potential to be integrated into a garlic root trimming machine to develop a fully automatic garlic root trimming and sorting robot.

Efficient oblivious database joins

A major algorithmic challenge in designing applications intended for secure remote execution is ensuring that they are oblivious to their inputs, in the sense that their memory access patterns do not leak sensitive information to the server. This problem is particularly relevant to cloud databases that wish to allow queries over the client's encrypted data. One of the major obstacles to such a goal is the join operator, which is non-trivial to implement obliviously without resorting to generic but inefficient solutions like Oblivious RAM (ORAM). We present an oblivious algorithm for equi-joins which (up to a logarithmic factor) matches the optimal O ( n log n ) complexity of the standard non-secure sort-merge join (on inputs producing O ( n ) outputs). We do not use use expensive primitives like ORAM or rely on unrealistic hardware or security assumptions. Our approach, which is based on sorting networks and novel provably-oblivious constructions, is conceptually simple, easily verifiable, and very efficient in practice. Its data-independent algorithmic structure makes it secure in various different settings for remote computation, even in those that are known to be vulnerable to certain side-channel attacks (such as Intel SGX) or with strict requirements for low circuit complexity (like secure multiparty computation). We confirm that our approach is easily realizable by means of a compact implementation which matches our expectations for performance and is shown, both formally and empirically, to possess the desired security characteristics.

An O(1) time complexity sorting network for small number of inputs with hardware implementation

The sorting algorithms have found applications in various research fields including image and video processing. High speed sorting is important in real-time applications, such as real-time image processing. Two properties are criterion for sorting networks: the number of steps (speed) and the number of comparators (efficiency). In this paper, we have proposed a method to decrease the number of steps. We introduce a new method for sorting an unordered sequence, which is based on the graph theory concept,and contrary to the conventional sorting networks, it consists of graph edge calculators rather than compare-and-swaps. An outstanding feature of the proposed method is that for small number of inputs, its number of steps is independent of the number of inputs that denotes it orders N inputs in O(1) steps. Moreover, the proposed method surpasses the previous ones in term of speed; it just needs two steps to sort a sequence. In the first step, all the inputs are compared with each other, and in the second step, the results of comparisons direct the inputs to the right outputs. To justify the functionality, the proposed method is simulated with the Modelsim-Altera and implemented on a Cyclone IV FPGA platform. Simulation results indicate that in comparison with the Bather's Bitonic mergesort, which is known to be the fastest algorithm, the proposed method while requires 80% more LEs, consumes 52% less memory and achieves 73% more throughput. Furthermore, the Bitonic mergesort can only accept a power of 2 number of inputs, while the proposed method does not hold such a limitation.

A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher’s Sorting Network

Eigenvalue Decomposition (EVD) and Singular Value Decomposition (SVD) are two crucial transformations in many signal processing applications. The main drawback of these algorithms is their computationally intensive nature which prevents them to be efficiently exploited in high-performance, real-time and mobile applications. By extracting the inherent parallelism of the Jacobi SVD, a new parallel data distribution and access pattern for this algorithm is proposed first. Based on the proposed parallel data distribution, a novel shared-memory architecture is then proposed to support EVD/SVD computation in a high-performance and scalable manner. A new Multistage Interconnection Network based on Batcher’s odd-even merge sorting network is developed and exploited in the architecture to preserve its performance and scalability by simultaneously connecting different numbers of processing elements to the system memory hierarchy in a parallel conflict-free manner. The proposed architecture can be configured to compute EVD/SVD of matrices of arbitrary size, with different numbers of processing elements achieving a linear speed-up. The synthesis results in a 90 nm technology show that the system with one, two, and four processing elements achieves a throughput of 1.81, 3.63, and 7.26 million EVD/SVD’s per second, respectively with a frequency of 813 MHz for an $8\times 8$ matrix.

An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs

Sorting is essential for many scientific and data processing problems. It is significant to improve the efficiency of sorting. Taking advantage of specialized hardware, parallel sorting, e.g., sorting networks and linear sorters, implements sorting in lower time complexity. However, most of them are designed based on the parallelization of algorithms, lacking consideration of specialized hardware structures. In this article, we propose an extended nonstrict partially ordered set-based configurable linear sorter on field-programmable gate arrays (FPGAs). First, we extend nonstrict partial order to the binary tuple and n -tuple nonstrict partial orders. Then, the linear sorting algorithm is defined based on them, with the consideration of hardware performance. It has 4 N/n time complexity varying from 4 to 2 N as the tuple size varies. The number of comparisons reduces to N /2 in binary tuple-based sorting, which is half of the state-of-the-art insertion linear sorting. Finally, we implement the linear sorter on FPGAs. It consists of multiple customizable micro-cores, named sorting units (SUs). The SU packages the storage and comparison of the tuple. All the SUs are connected into a chain with simple communication, which makes the sorter fully configurable in length, bandwidth, and throughput. They also act the same in each clock cycle, so that the achieved frequency of the sorter improves. In our experiment, the sorter achieves at most 660-MHz frequency, 5.6 Gb/s throughput, and 87 times speed-up compared with the quick sort algorithm on general processors.

Efficient Model-Based Diagnosis of Sequential Circuits

In Model-Based Diagnosis (MBD), we concern ourselves with the health and safety of physical and software systems. Although we often use different knowledge representations and algorithms, some tools like satisfiability (SAT) solvers and temporal logics, are used in both domains. In this paper we introduce Finite Trace Next Logic (FTNL) models of sequential circuits and propose an enhanced algorithm for computing minimal-cardinality diagnoses. Existing state-of-the-art satisfiability algorithms for minimal diagnosis use Sorting Networks (SNs) for constraining the cardinality of the diagnostic candidates. In our approach we exploit Multi-Operand Adders (MOAs). Based on extensive tests with ISCAS-89 circuits, we found that MOAs enable Conjunctive Normal Form (CNF) encodings that are significantly more compact. These encodings lead to 19.7 to 67.6 times fewer variables and 18.4 to 62 times fewer clauses. For converting an FTNL model to CNF, we could achieve a speed-up ranging from 6.2 to 22.2. Using SNs fosters 3.4 to 5.5 times faster on-line satisfiability checking though. This makes MOAs preferable for applications where RAM and off-line time are more limited than on-line CPU time.

Reinforced sorting networks for particle physics analyses

Deep learning architectures in particle physics are often strongly dependent on the order of their input variables. We present a two-stage deep learning architecture consisting of a network for sorting input objects and a subsequent network for data analysis. The sorting network (agent) is trained through reinforcement learning using feedback from the analysis network (environment). The optimal order depends on the environment and is learned by the agent in an unsupervised approach. Thus, the two-stage system can choose an optimal solution which is not known to the physicist in advance. We present the new approach and its application to the signal and background separation in top-quark pair associated Higgs boson production.

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

Friedrichs et al. (TC 2018) showed that metastability can be contained when sorting inputs arising from time-to-digital converters, i.e., measurement values can be correctly sorted without resolving metastability using synchronizers first. However, this work left open whether this can be done by small circuits. We show that this is indeed possible, by providing a circuit that sorts Gray code inputs (possibly containing a metastable bit) and has asymptotically optimal depth and size. Our solution utilizes the parallel prefix computation (PPC) framework (JACM 1980). We improve this construction by bounding its fan-out by an arbitrary $f\geq 3$ f ≥ 3 , without affecting depth and increasing circuit size by a small constant factor only. Thus, we obtain the first PPC circuits with asymptotically optimal size, constant fan-out, and optimal depth. To show that applying the PPC framework to the sorting task is feasible, we prove that the latter can, despite potential metastability, be decomposed such that the core operation is associative. We obtain asymptotically optimal metastability-containing sorting networks. We complement these results with simulations, independently verifying the correctness as well as small size and delay of our circuits. Proofs are omitted in this version; the article with full proofs is provided online at http://arxiv.org/abs/1911.00267 .

DSL-Based Hardware Generation with Scala

We present a hardware generator for computations with regular structure including the fast Fourier transform (FFT), sorting networks, and others. The input of the generator is a high-level description of the algorithm; the output is a token-based, synchronized design in the form of RTL-Verilog. Building on prior work, the generator uses several layers of domain-specific languages (DSLs) to represent and optimize at different levels of abstraction to produce a RAM- and area-efficient hardware implementation. Two of these layers and DSLs are novel. The first one allows the use and domain-specific optimization of state-of-the-art streaming permutations. The second DSL enables the automatic pipelining of a streaming hardware dataflow and the synchronization of its data-independent control signals. The generator including the DSLs are implemented in Scala, leveraging its type system, and uses concepts from lightweight modular staging (LMS) to handle the constraints of streaming hardware. Particularly, these concepts offer genericity over hardware number representation, including seamless switching between fixed-point arithmetic and FloPoCo generated IEEE floating-point operators, while ensuring type-safety. We show benchmarks of generated FFTs, sorting networks, and Walsh-Hadamard transforms that outperform prior generators.

A Sorting Network on Trees

Sorting networks are a class of parallel oblivious sorting algorithms. Not only do they have interesting theoretical properties but they can be fabricated. A sorting network is a sequence of parallel compare-exchange operations using comparators which are grouped into stages. This underlying graph defines the topology of the network. The majority of results on sorting networks concern the unrestricted case where the underlying graph is the complete graph. Prior results are also known for paths, hypercubes, and meshes. In this paper we introduce a sorting network whose underlying topology is a tree and formalize the concept of sorting networks on a restricted graph topology by introducing a new parameter for graphs called its sorting number. The main result of the paper is a description of an [Formula: see text] depth sorting network on a tree with maximum degree [Formula: see text].

Circular support in random sorting networks

A sorting network is a shortest path from $12 \cdots n$ to $n \cdots 2 1$ in the Cayley graph of the symmetric group generated by adjacent transpositions. For a uniform random sorting network, we prove that in the global limit, particle trajectories are supported on $\pi$-Lipschitz paths. We show that the weak limit of the permutation matrix of a random sorting network at any fixed time is supported within a particular ellipse. This is conjectured to be an optimal bound on the support. We also show that in the global limit, trajectories of particles that start within distance $\epsilon$ of the edge are within $\sqrt{2\epsilon}$ of a sine curve in uniform norm.

RESOURCE-INDEPENDENT REPRESENTATION OF SORTING NETWORKS IN Set@l PROGRAMMING LANGUAGE

The development of scalable parallel programs for high-performance computer systems with reconfigurable and hybrid architectures is an important problem in the field of modern supercomputer engineering. Resource-independent applied software in the high-level COLAMO programming language describes only the limited number of the algorithm implementations for some configurations due to the inductive principle of the information graph forming. However, the creation of efficient resource-independent parallel software requires programming tool that supports both induction and reduction of calculations. To solve the problem, we propose the application of the Set@l programming language based on the aspect-oriented programming paradigm and set-theoretical code representation. According to the aspect-oriented concept, Set@l describes an algorithm for the problem solution and its parallelizing and other implementation features as separated program modules – source code and various aspects. The programming language being considered has much in common with traditional set-theory-based languages such as SETL, SETLX and SETL2, but Set@l introduces the essential classification of collections by parallelism, definiteness, orderliness and other criteria. In contrast to the high-level COLAMO programming language, Set@l specifies the full information graph of a computational problem in the absolutely parallel form and describes the reduction principles for all configurations of a computer system as independent aspects of a program. In this paper, we demonstrate that the aspect-oriented sorting program in the Set@l language defines different types of quadratic sorting networks and various methods of their partition and reduction.

Performance Assessment of Different VLSI Architectures for Data Comparators for Cost Effective Sorting Networks

Noise removal is one of the major requirements in image, speech and signal processing applications. Impulse noise removal in image processing uses median filters. For edge preservation in image processing this acts as one of the best alternative non-linear technique to linear filtering. Real time hardware implementation of median filters has major concern of sorting networks. Efficient VLSI implementation of sorting network in terms of hardware complexity is of greater importance. This work provides a comparison of existing six data comparators and also proposes three modified data comparators in terms of their hardware complexity, area, power and speed. All the comparators were designed using verilog HDL and were targeted for xa6slx4-3-csg225using Xilinx ISE 9.2i FPGA design suite. From the results Modified Twos Complement Based Data Comparator is the minimum area required architecture with maximum combinational path delay and also with minimum number of LUTs used. The drawback of this architecture is the maximum memory requirement. The Modified Multiplexer Based Data Comparator and Modified Decoder Based Data Comparator architectures are suitable for memory efficient design.

VLSI architecture for Vasanth sorting to denoise image with minimum comparators

An efficient VLSI architecture for minimized sorting network (Vasanth sorting) in rank ordering application to remove salt and pepper noise is proposed. The basic operation in salt and pepper noise removal is rank ordering. In this work, a novel 2D sorting technique referred to as Vasanth sorting is proposed for a fixed 3 × 3 window. Vasanth sorting requires only 25 comparators to sort 9 elements of the window. A parallel architecture is developed for Vasanth sorting with 25 comparators. The processing element of the parallel architecture is an 8-bit data comparator (Two cell comparator). The performance of the proposed sorting technique is compared with the different sorting technique which is targeted for XCV1000-5bg560 on XILINX 7.1i and xc7v2000t-2flg1925 Xilinx 14.7 project manager respectively with Modelsim 10.4a for simulation and XST compiler tool for synthesis using VHDL. It was found that the parallel architecture developed for Vasanth sorting requires the only ¼ of the area in FPGA when compared to existing sorting techniques. The combinational delay of the proposed architecture was also twice as less like their counterparts. The power consumption of the logic was 7mw. Hence the above performances make Vasanth sorting a better choice compared to existing techniques for rank ordering.

Geometry of Permutation Limits

This paper initiates a limit theory of permutation valued processes, building on the recent theory of permutons. We apply this to study the asymptotic behaviour of random sorting networks. We prove that the Archimedean path, the conjectured limit of random sorting networks, is the unique path from the identity to the reverse permuton having minimal energy in an appropriate metric. Together with a recent large deviations result (Kotowski, 2016), it implies the Archimedean limit for the model of relaxed random sorting networks.