Solid State Drives Research Articles

Procedures for Digital Forensics and Incident Response on Including Data Integrity Constraints on Solid-State Drives (SSD) - A Literature Review

Procedures for Digital Forensics and Incident Response on Including Data Integrity Constraints on Solid-State Drives (SSD) - A Literature Review

Embedded Transaction Support Inside SSD With Small-Capacity Non-Volatile Disk Cache

Flash-based Solid State Drives (SSDs) have proved to be ideal devices that support embedded transaction protocols inside SSDs. Existing embedded transaction protocols effectively improve transaction throughput, but still incur high transaction overhead and long recovery time. In this paper, we propose a new embedded transaction protocol called Non-volatile Cache Transaction (NVCTX). NVCTX reduces transaction overhead and provides fast recovery by leveraging the small-capacity NVM-based disk cache from two aspects. First, we store transactional metadata, which is of small amount but is frequently accessed, in the NVM-based disk cache rather than in the flash memory. Second, we introduce two techniques to improve the performance when the capacity of the NVM-based disk cache is very limited. We have implemented NVCTX on a real hardware board, and modified ext4 file system and NVMe driver to be compatible with the transactional interfaces provided by NVCTX. For comparison, we implement other four protocols in the firmware. Evaluations using DBMS and file system workloads show that, compared to other protocols, NVCTX improves transaction throughput by up to 136.5%, 9.4%, 131.6% and 29.9%, reduces write traffic to flash memory by up to 42.8%, 4.1%, 62.4%, 31.2%, and shortens recovery time to 1/2574, 1/2559, 1/95 and 1/2 respectively.

A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration

Nonvolatile memory express (NVMe) is a high-performance and scalable PCI express (PCIe)-based interface for the host software communicating with NVMs, including NAND Flash and the storage class memories (SCMs). NVMe solid-state drives (SSDs) have been deployed in cloud platforms and data-centers for a variety of I/O intensive applications due to their performance benefits compared to SATA/SAS SSDs. Considering the design flexibility, firmware-based NVMe controllers are typically used in Flash-based NVMe SSDs but may occupy a significant portion of processor resources and power consumption to achieve high performance. Moreover, the firmware component can be a critical performance bottleneck for SCMs that are an order-of-magnitude faster than Flash. To address these challenges, hardware-accelerated NVMe controllers have emerged in both industry and academia. The commercial hardware controllers are confidential, whereas current academic studies still spare much room for architecture innovations. In this article, we propose an opensource ultralow-latency and high-throughput NVMe controller with a highly parallel, pipelined, and scalable architecture that accommodates one admin controller and multiple fully hardware-automated I/O controllers. We perform extensive empirical performance evaluations concerning the NVMe I/O size, queue depth, queue number, read-to-write ratio, and access pattern. The maximum read/write bandwidth can achieve 7.0 GB/s, accounting for 89&#x0025; of the PCIe bandwidth. The 4-KB-sized read/write throughput can attain 1.7 million I/O operations per second (MIOPS), whereas the average latency is merely 2.4 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>/3.2 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>. Compared to state-of-the-art NVMe controllers in academia, the 4-KB-sized read/write bandwidth of our controller reaches <inline-formula> <tex-math notation="LaTeX">$2.2 \times /2.3\times $ </tex-math></inline-formula> as high and the latency is <inline-formula> <tex-math notation="LaTeX">$5.1 \times /4.9\times $ </tex-math></inline-formula> lower.

Automatic Stream Identification to Improve Flash Endurance in Data Centers

The demand for high performance I/O in Storage-as-a-Service (SaaS) is increasing day by day. To address this demand, NAND Flash-based Solid-state Drives (SSDs) are commonly used in data centers as cache- or top-tiers in the storage rack ascribe to their superior performance compared to traditional hard disk drives (HDDs). Meanwhile, with the capital expenditure of SSDs declining and the storage capacity of SSDs increasing, all-flash data centers are evolving to serve cloud services better than SSD-HDD hybrid data centers. During this transition, the biggest challenge is how to reduce the Write Amplification Factor (WAF) as well as to improve the endurance of SSD since this device has a limited program/erase cycles. A specified case is that storing data with different lifetimes (i.e., I/O streams with similar temporal fetching patterns such as reaccess frequency) in one single SSD can cause high WAF, reduce the endurance, and downgrade the performance of SSDs. Motivated by this, multi-stream SSDs have been developed to enable data with a different lifetime to be stored in different SSD regions. The logic behind this is to reduce the internal movement of data—when garbage collection is triggered, there are high chances of having data blocks with either all the pages being invalid or valid. However, the limitation of this technology is that the system needs to manually assign the same streamID to data with a similar lifetime. Unfortunately, when data arrives, it is not known how important this data is and how long this data will stay unmodified. Moreover, according to our observation, with different definitions of a lifetime (i.e., different calculation formulas based on selected features previously exhibited by data, such as sequentiality, and frequency), streamID identification may have varying impacts on the final WAF of multi-stream SSDs. Thus, in this article, we first develop a portable and adaptable framework to study the impacts of different workload features and their combinations on write amplification. We then propose a feature-based stream identification approach, which automatically co-relates the measurable workload attributes (such as I/O size, I/O rate, and so on.) with high-level workload features (such as frequency, sequentiality, and so on.) and determines a right combination of workload features for assigning streamIDs . Finally, we develop an adaptable stream assignment technique to assign streamID for changing workloads dynamically. Our evaluation results show that our automation approach of stream detection and separation can effectively reduce the WAF by using appropriate features for stream assignment with minimal implementation overhead.

A modeling approach for estimating performance and energy consumption of storage systems

Improvements in data storage may be constrained by the lower performance of hard disk drives (HDD) and the higher cost per gigabyte of solid-state drives (SSD). To mitigate these issues, hybrid storage architectures have been conceived. Some works evaluate the performance of storage architectures, but energy consumption is usually neglected and not simultaneously evaluated with performance. This paper presents an approach based on generalized stochastic Petri nets (GSPN) for performance and energy consumption evaluation of individual and hybrid storage systems. The proposed models can represent distinct workloads and also estimate throughput, response time and energy consumption of storage systems. Experiments based on industry-standard benchmarks are adopted to demonstrate the feasibility of the proposed approach.

RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection

Due to the so-called curse of dimensionality and increase in the size of databases, there is an ever-increasing demand for computing resources and memory bandwidth when performing the k-nearest neighbors (kNNs) algorithm, resulting in a slow-down to process large datasets. This work presents an OpenCL-based framework for accelerating the kNN algorithm on field-programmable gate arrays (FPGAs) benefiting from the random projection dimensionality reduction. The proposed RPkNN framework includes two compute modules implementing a throughput-optimized hardware architecture based on random projection and the kNN algorithm and a host program facilitating easy integration of the compute modules in the existing applications. RPkNN also utilizes a new buffering scheme tailored to random projection and the kNN algorithm. The proposed architecture enables parallel kNN computations with a single memory channel and takes advantage of the sparsity features of the input data to implement a highly optimized and parallel implementation of random projection. We employ a computation storage device (CSD) to directly access the high-dimensional data on non-volatile memory express (NVMe) solid state drive (SSD) and store and reuse the compressed and low-dimensional data on the FPGA dynamic random access memory (DRAM), hence eliminating data transfers to the host DRAM. We compare RPkNN implemented on the Samsung SmartSSD CSD with the kNN implementation of the scikit-learn library running on an Intel Xeon Gold 6154 CPU. The experimental results show that the proposed RPkNN solution achieves, on average, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$26\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46\times $ </tex-math></inline-formula> higher performance across different dimensions per a single kNN computation for the SIFT1M and GIST1M databases, respectively. Finally, RPkNN is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> faster than the similar FPGA-based reference method.

Selective Power-Loss-Protection Method for Write Buffer in ZNS SSDs

Most SSDs (solid-state drives) use an internal DRAM (Dynamic Random Access Memory) to improve the I/O performance and extend SSD lifespan by absorbing write requests. However, this volatile memory does not guarantee the persistence of buffered data in the event of sudden power-off. Therefore, highly reliable enterprise SSDs employ power-loss-protection (PLP) logic to ensure the durability of buffered data using the back-up power of capacitors. The SSD must provide enough capacitors for the PLP in proportion to the size of the volatile buffer. Meanwhile, emerging ZNS (Zoned Namespace) SSDs are attracting attention because they can support many I/O streams that are useful in multi-tenant systems. Although ZNS SSDs do not use an internal mapping table unlike conventional block-interface SSDs, a large write buffer is required to provide many I/O streams. The reason is that each I/O stream needs its own write buffer for write buffering where the host can allocate separate zones to different I/O streams. Moreover, the larger capacity and more I/O streams the ZNS SSD supports, the larger write buffer is required. However, the size of the write buffer depends on the amount of capacitance, which is limited not only by the SSD internal space, but also by the cost. Therefore, in this paper, we present a set of techniques that significantly reduce the amount of capacitance required in ZNS SSDs, while ensuring the durability of buffered data during sudden power-off. First, we note that modern file systems or databases have their own solutions for data recovery, such as WAL (Write-ahead Log) and journal. Therefore, we propose a selective power-loss-protection method that ensures durability only for the WAL or journal required for data recovery, not for the entire buffered data. Second, to minimize the time taken by the PLP, we propose a balanced flush method that temporarily writes buffered data to multiple zones to maximize parallelism and preserves the data in its original location when power is restored. The proposed methods are implemented and evaluated by modifying FEMU (QEMU-based Flash Emulator) and RocksDB. According to experimental results, the proposed selective-PLP reduces the amount of capacitance by 50 to 90% while retaining the reliability of ZNS SSDs. In addition, the balanced flush method reduces the PLP latency by up to 96%.

Efficient Garbage Collection Algorithm for Low Latency SSD

Solid-state drives (SSDs) are rapidly replacing hard disk drives (HDDs) in many applications owing to their numerous advantages such as higher speed, low power consumption, and small size. NAND flash memories, the memory devices used for SSDs, require garbage collection (GC) operations to reclaim wasted storage space due to obsolete data. The GC is the major source of performance degradation because it greatly increases the latency for SSDs. The latency for read or write operations is sometimes significantly long if the operations are requested by users while GC operations are in progress. Reducing the frequency of GC invocation while maintaining the storage space requirement may be an ideal solution to remedy this problem, but there is a minimal number of GC operations to reserve storage space. The other approach is to reduce the performance overhead due to GC rather than reducing GC frequency. In this paper, following the latter approach, we propose a new GC scheme that reduces GC overhead by intelligently controlling the priorities among read/write and GC operations. The experimental results show the proposed scheme consistently improve the overall latency for various workloads.

Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory

Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage ( V th ) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed ( V th ) distribution, ( V th ) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.

Lifespan-based garbage collection to improve SSD's reliability and performance

Given the “out-of-place” nature of write mode, Solid State Drive (SSD) has to execute a garbage collection (GC) to reclaim the space of invalidated data and free flash blocks for new written data. However, the GC can incur the movements of valid data inside SSD, resulting in the problems such as write latency, write amplification, etc. The GC overheads of SSD depend not only on the current write pattern but also on how data have been already placed in SSD. If data can be classified by their lifetime when written to SSD, and the data with similar lifetime are written into the same flash block, we can select the block with the shortest expected lifespan as the victim block. Ideally, the victim block contains few valid data, implying there are few valid pages that need to be migrated during the GC process with greatly reduced overhead. In this paper, we propose and implement a GC method, called Lifespan-based GC, for SSDs based on the data lifetime, together with the I/O distribution and the dynamic flash memory allocation. The results show that for those applications with the data lifetime characteristics, the lifespan-based GC can effectively reduce the amount of valid pages migrated in GC process, thereby minimizing the write latency and write amplification caused by GC.

Read Refresh Scheduling and Data Reallocation against Read Disturb in SSDs

Read disturb is a circuit-level noise in flash-based Solid-State Drives (SSDs), induced by intensive read requests, which may result in unexpected read errors. The approach of read refresh (RR) is commonly adopted to mitigate its negative effects by unconditionally migrating all valid data pages in the RR block to another new block. However, routine RR operations greatly impact the I/O responsiveness of SSDs, because the processing on normal I/O requests must be blocked at the same time. To further reduce the negative effects of read refresh, this article proposes a read refresh scheduling and data reallocation method to deal with two primary issues with respect to an RR operation, including where to place data pages and when to trigger page migrations. Specifically, we first construct a data reallocation model to match the data pages in the RR block and the destination blocks for addressing the issue of where to place the data. The model considers not only the read hotness of pages in the RR block, but also the accumulated read counts of the destination blocks. Moreover, for addressing the issue of when to trigger data migrations, we build a timing decision model to determine the time points for completing page migrations by considering the factors of the intensity of I/Os and the disturb situation on the RR block. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed RR scheduling and data reallocation mechanism can noticeably reduce the read errors by more than 10.3% , on average, and the long-tail latency by between 43.9% and 64.0% at the 99.99th percentile, in contrast to state-of-the-art methods.

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, because of the nature of the lamination process, the frequency of error occurrence varies depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of flash memory write/erase (Program/Erasure) operations increases. Error correction code (ECC) is used for error correction in the majority of flash-based storage devices, such as SSDs (Solid State Drive). As this method provides a constant level of data protection for all-flash memory pages, there is a limitation in 3D-NAND flash memory, where the error rate varies depending on physical location. Consequently, in this paper, pages and layers with varying error rates are classified into clusters using the k-means machine-learning algorithm, and each cluster is assigned a different level of data protection strength. We classify pages and layers based on the number of error occurrences measured at the end of the endurance test, and for areas vulnerable to errors, it is shown as an example of providing differentiated data protection strength by adding parity data to the stripe. Furthermore, areas vulnerable to retention errors are identified based on retention error rates, and bit error rates are significantly reduced through our hot/cold-aware data placement policy. We show that the proposed differential data protection and hot/cold-aware data placement policies improve the reliability and lifespan of 3D-NAND flash memory compared with the existing ECC- or RAID-type data protection scheme.

Penerapan Text Network Analysis Dalam Menganalisis Pendapat Customer Product Patriot di Shopee

E-commerce has changed the buying and selling process and the way people interact via the internet. One company that uses e-commerce is PT Patriot Memory Indonesia. PT Patriot Memory Indonesia sells well-known computer peripherals, including the Solid State Drive (SSD). PT Patriot Memory Indonesia wants to analyze customer feedback regarding SSD products sold in e-commerce, namely Shopee by using Text Network Analysis (TNA) which is one part of social computing. Social computing is a science that focuses on social behavior and social contexts using computing systems. One of the tools of social computing, namely Text Network Analysis (TNA), is a research technique that focuses on identifying and comparing network relationships between words, sentences, and systems to model interactions that generate new knowledge or information. In this study, TextNetwork Analysis will show consumer perceptions through the feedback it provideson buyer reviews. The opinions expressed by consumers in buyer reviews can be analyzed so that they can connect each word and create associations of consumer perceptions of a product. Thus, it can be seen the aspects that must be addressed by the company to improve consumer perceptions. The problem analyzed is the development of social computing in analyzing big data. Can the company take advantage of this information so that they know the perceptions of their consumers through the information in the customer feedback at Shopee. Through Text Network Analysis in social computing, researchers will know the association of each word of consumer perception and can see the perception that has the highest degree of a product and see its relationship with other perceptions. This study looks at consumer perceptions of Patriot SSD products at Shopee. The results of this study can help provide customer feedback information to PT Patriot Memory Indonesia.

Multi-Instance Adversarial Learning Domain Adaptation Network for Failure Prediction of Unlabeled Solid State Drives

Recently, with the large-scale application of solid state drives (SSDs), the failure of SSDs has become the main reliability issue in the data centers. SSDs manufacturers developed self-monitoring, analysis, and reporting technology (SMART) to indicate the health status of SSDs. However, for the newly enabled and the new types of SSDs in the data centers, lacking enough labeled data will be a critical problem, making failure prediction for SSDs a difficult task. To this end, this paper proposes a multi-instance adversarial learning domain adaptation network for coping with this task. A multi-instance learning method with an attention mechanism is designed to solve the problem of features extraction from unlabeled data by assigning weights to features over the lifespan. Moreover, the distribution differences between different SSDs models prevent the knowledge of the labeled information from being used for failure prediction of the unlabeled data, an adversarial domain adaptation method is used to align the distributions. Finally, the proposed method is verified on Alibaba’s dataset and shows much better performance than other methods.

An Efficient Block Address Transformation Scheme in Block Layer for Flash-Based SSDs

Flash-based solid state drives (SSDs) are widely adopted in both industry and the academia since SSDs offer higher performance, lower latency, and lower power consumption compared with traditional hard disk drives (HDDs). Unfortunately, the performance of SSDs can be affected by I/O access patterns. For example, random I/O operation degrades the SSD performance compared with sequential I/O operation since the random I/O operation reduces the spatial locality and increases garbage collection (GC) overhead. To handle this issue, in this article, we propose an efficient block address transformation scheme in the block layer to improve both performance and portability. To do this, we first transform random access patterns to sequential access patterns by sequentializing the block addresses in the block layer. Second, we devise a mapping table for managing transformed block addresses. Third, we support correct read operations and transaction processing for updating the mapping table to avoid sacrificing the consistency. Finally, we provide a cleaning scheme to reclaim invalid data generated by the transformed sequential access. This scheme increases spatial locality, reduces GC overhead, and operates well on any file systems or devices. Experimental results show the proposed scheme improves performance by up to 2x, 1.86x, 2.15x, and 42.8% compared with existing scheme in the case of diverse file systems such as EXT4, XFS, BTRFS, and F2FS, respectively.

Meta-Block: Exploiting Cross-Layer and Direct Storage Access for Decentralized Blockchain Storage Systems

Decentralized storage systems such as blockchain storage applications adopt the distributed storage technology and use distributed storage nodes to store the persistent data. For each off-chain storage node, key-value (KV) stores are normally used to manage data. As the most common data structure for KV store, Log Structured Merge Tree (LSM-Tree) eliminates random write operations and keeps acceptable read performance. Although LSM-Tree-based decentralized storage system can provide a secure and reliable storage platform, the unique feature of blockchain applications is not fully exploited. In blockchain storage applications, the generation of keys for KV stores is based on the encrypted data, and the key determines the allocation of data. Since the granularity for a read/write request at the level of blockchain storage platform is much smaller than that at the level of LSM-Tree or flash memory, a physical block in a solid-state drive (SSD) could be filled with data from different system users. This mixture of workloads will lead to the inefficient usage of physical spaces in the SSD and cause extra compaction operations for LSM-Tree. This paper presents <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Meta-Block</i> , a cross-layer and efficient storage management strategy for decentralized blockchain storage applications. Meta-Block utilizes rich functionalities provided by the system infrastructure of open-channel SSD to provide direct storage accesses for the off-chain storage node. The objective is to capture the features of blockchain storage applications and reduce unnecessary read and write operations across different storage layers. As a cross-layer design, Meta-Block redesigns the organization of LSM-Tree, which can effectively reduce the write amplification. We also design a data prefetching strategy to speed up the indexing and enable direct storage access. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that Meta-Block can effectively reduce the write amplification and extend the lifetime of SSDs in comparison with representative schemes.

EddySuperblock: Improving NAND Flash Efficiency and Lifetime by Endurance-Driven Dynamic Superblock Management

Solid-state drives (SSDs) are widely used in current storage systems. SSD manufacturers usually aggregate physical blocks across planes into one superblock to improve SSD performance. However, due to the wear endurance variations among blocks and pages, the standard superblock scheme leads to lifetime and space waste of SSDs. Superblock granularity also causes higher and more uncertain garbage collection overhead. To address these problems, this work proposes endurance-driven dynamic superblock management called EddySuperblock to provide a longer lifetime and higher space utilization with a faster and deterministic response time, which designs a dynamic superblock organization strategy that links free strong blocks into one superblock according to the real-time wear index of each block and introduces page-level wear management to further unlock the lifetime potential of pages. To reduce the high garbage collection overhead caused by superblocks, a nonblocking parallel garbage collection policy is proposed, which can reclaim space and serve requests simultaneously with low overhead. We conduct a set of experiments on a real hardware experiment platform. Both the proposed EddySuperblock and representative superblock schemes have been implemented on the experiment platform. The experimental results show that our scheme greatly reduces the average system response time by 47.6% and prolongs the lifetime by 75.6% compared with the state-of-the-art superblock scheme, and the final-state flash utilization reaches 95.4%. In the end, this article presents the application status of our work in real-world scenarios.

Analysis and Mitigation of Patterned Read Collisions in Flash SSDs

A modern flash solid-state drive (SSD) achieves superb throughput by accessing its flash memory dies in parallel. To obtain parallelism in processing writes, the flash translation layer (FTL) of an SSD is allowed to allocate physical pages from idle dies or dies with low loads. However, since the die that holds the page to be read is determined in advance, when multiple read requests head for one die, read collisions occur, and the read operations involved in the collisions must be serialized. These read collisions lead to a significant prolongation of read latency and, thus the degradation of throughput. As the density of flash dies increases, more pages are stored on a die, which is expected to result in more frequent read collisions. Unlike the write collisions that the DRAM buffer can absorb, read collisions directly affect user-experienced latency. Therefore, the severity of the problem is further increased. In this paper, we identify the impact of read collisions on performance with real-world traces. We also propose an approach that distinguishes patterned read collisions from accidental ones and mitigates the performance impact of patterned read collisions. By replicating frequently occurring pages involved in patterned read collisions, the proposed approach improves the average and tail read latency of an SSD. The evaluation through simulation with the 34 MSR Cambridge traces showed that 12 traces out of 34 earned read performance improvement larger than 10% and up to 37%. In addition, the tail read latency of 15 traces was reduced by at least 20% and by up to 53%. Only two traces showed negligible degradation in average and tail read latency by around 1%.

Design and Implementation of a Modular and Scalable Research Platform for Ultrasound Computed Tomography.

Increasing attention has been attracted to the research of ultrasound computed tomography (USCT). This article reports the design considerations and implementation details of a novel USCT research system named UltraLucid, which aims to provide a user-friendly platform for researchers to develop new algorithms and conduct clinical trials. The modular design strategy is adopted to make the system highly scalable. A prototype has been assembled in our laboratory, which is equipped with a 2048-element ring transducer, 1024 transmit (TX) channels, 1024 receive (RX) channels, two servers, and a control unit. The prototype can acquire raw data from 1024 channels simultaneously using a modular data acquisition and a transfer system, consisting of 16 excitation and data acquisition (EDAQ) boards. Each EDAQ board has 64 independent TX and RX channels and 4-Gb Ethernet interfaces for raw data transmission. The raw data can be transferred to two servers at a theoretical rate of 64 Gb/s. Both servers are equipped with a 10.9-TB solid-state drive (SSD) array that can store raw data for offline processing. Alternatively, after processing by onboard field-programmable gate arrays (FPGAs), the raw data can be processed online using multicore central processing units (CPUs) and graphics processing units (GPUs) in each server. Through control software running on the host computer, the researchers can configure parameters for transmission, reception, and data acquisition. Novel TX-RX scheme and coded imaging can be implemented. The modular hardware structure and the software-based processing strategy make the system highly scalable and flexible. The system performance is evaluated with phantoms and in vivo experiments.

노트북 컴퓨터에 장착된 SSD의 낙하 실험과 유한요소 해석을 활용한 취약부 및 수명 예측

This study demonstrates a method for predicting the vulnerable location and fatigue life of an SSD (solid state drive) mounted on a notebook computer in a drop environment. In order to construct the drop environment of a notebook computer, a jig with the same weight and structure as the actual computer was used. The SSD was fixed in the same location as it would be on a notebook computer, and a drop experiment was performed. A drop analysis was performed by developing a finite element model of the notebook computer with the SSD. Additionally, we analyzed the effects of secondary contact between the SSD and other components. The vulnerable location was determined using the stress analysis results from the solder ball of the SSD. Using the analysis results and the Coffin -Manson equation, the fatigue life of the SSD in a drop environment was predicted.