Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory

Compared to planar NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. Our goal is to (1)~identify and understand these new error characteristics of 3D NAND flash memory, and (2)~develop new techniques to mitigate prevailing 3D NAND flash errors. \chIIIn this paper, we perform a rigorous experimental characterization of real, state-of-the-art 3D NAND flash memory chips, and identify three new error characteristics that were not previously observed in planar NAND flash memory, but are fundamental to the new architecture of 3D NAND flash memory. \beginenumerate [leftmargin=13pt] ıtem 3D NAND flash memory exhibits layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different. We are the first to provide detailed experimental characterization results of layer-to-layer process variation in real flash devices in open literature. Our results show that the raw bit error rate in the middle layer can be 6× the error rate in the top layer. ıtem 3D NAND flash memory experiences \emphearly retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming, but then increases at a much slower rate. We are the first to perform an extended-duration observation of early retention loss over the course of 24~days. Our results show that the retention error rate in a 3D NAND flash memory block quickly increases by an order of magnitude within $\sim$3 hours after programming. ıtem 3D NAND flash memory experiences retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells. Our results show that charge leaks at a lower rate (i.e., the retention loss speed is slower) when the neighboring cell is in a state that holds more charge (i.e., a higher-voltage state). \endenumerate Our experimental observations indicate that we must revisit the error models and error mitigation mechanisms devised for planar NAND flash, as they are no longer accurate for 3D NAND flash behavior. To this end, we develop \emphnew analytical model\chIs of (1)~the layer-to-layer process variation in 3D NAND flash memory, and (2)~retention loss in 3D NAND flash memory. Our models estimate the raw bit error rate (RBER), threshold voltage distribution, and the \emphoptimal read reference voltage (i.e., the voltage at which RBER is minimized when applied during a read operation) for each flash page. Both models are useful for developing techniques to mitigate raw bit errors in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, LaVAR, reduces process variation by fine-tuning the read reference voltage independently for each layer. Our second technique, LI-RAID, improves reliability by changing how pages are grouped under the RAID (Redundant Array of Independent Disks) error recovery technique, using information about layer-to-layer process variation to reduce the likelihood that the RAID recovery of a group could fail significantly earlier during the flash lifetime than recovery of other groups. Our third technique, ReMAR, reduces retention errors in 3D NAND flash memory by tracking the retention age of the data using our retention model and adapting the read reference voltage to data age. Our fourth technique, ReNAC, adapts the read reference voltage to the amount of retention interference to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash manufacturer wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%. For more information on our new experimental characterization of modern 3D NAND flash memory chips and our proposed models and techniques, please refer to the full version of our paper~\citeluo.pomacs18.

Compared to planar NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. Our goal is to (1)~identify and understand these new error characteristics of 3D NAND flash memory, and (2)~develop new techniques to mitigate prevailing 3D NAND flash errors. \chIIIn this paper, we perform a rigorous experimental characterization of real, state-of-the-art 3D NAND flash memory chips, and identify three new error characteristics that were not previously observed in planar NAND flash memory, but are fundamental to the new architecture of 3D NAND flash memory. \beginenumerate [leftmargin=13pt] ıtem 3D NAND flash memory exhibits layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different. We are the first to provide detailed experimental characterization results of layer-to-layer process variation in real flash devices in open literature. Our results show that the raw bit error rate in the middle layer can be 6× the error rate in the top layer. ıtem 3D NAND flash memory experiences \emphearly retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming, but then increases at a much slower rate. We are the first to perform an extended-duration observation of early retention loss over the course of 24~days. Our results show that the retention error rate in a 3D NAND flash memory block quickly increases by an order of magnitude within $\sim$3 hours after programming. ıtem 3D NAND flash memory experiences retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells. Our results show that charge leaks at a lower rate (i.e., the retention loss speed is slower) when the neighboring cell is in a state that holds more charge (i.e., a higher-voltage state). \endenumerate Our experimental observations indicate that we must revisit the error models and error mitigation mechanisms devised for planar NAND flash, as they are no longer accurate for 3D NAND flash behavior. To this end, we develop \emphnew analytical model\chIs of (1)~the layer-to-layer process variation in 3D NAND flash memory, and (2)~retention loss in 3D NAND flash memory. Our models estimate the raw bit error rate (RBER), threshold voltage distribution, and the \emphoptimal read reference voltage (i.e., the voltage at which RBER is minimized when applied during a read operation) for each flash page. Both models are useful for developing techniques to mitigate raw bit errors in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, LaVAR, reduces process variation by fine-tuning the read reference voltage independently for each layer. Our second technique, LI-RAID, improves reliability by changing how pages are grouped under the RAID (Redundant Array of Independent Disks) error recovery technique, using information about layer-to-layer process variation to reduce the likelihood that the RAID recovery of a group could fail significantly earlier during the flash lifetime than recovery of other groups. Our third technique, ReMAR, reduces retention errors in 3D NAND flash memory by tracking the retention age of the data using our retention model and adapting the read reference voltage to data age. Our fourth technique, ReNAC, adapts the read reference voltage to the amount of retention interference to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash manufacturer wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%. For more information on our new experimental characterization of modern 3D NAND flash memory chips and our proposed models and techniques, please refer to the full version of our paper~\citeluo.pomacs18.

This chapter introduces the design of three-dimensional (3D) NAND flash memory with the implications from the system side. For conventional two-dimensional (2D) scaling, it is facing various limitations such as lithography cost and cell-to-cell coupling interference. To sustain the trend of bit-cost reduction beyond 10 nm technology node, 3D NAND flash memory is considered as the next generation technique. Further, emerging memories called storage-class memories (SCMs) such as resistive RAM (ReRAM), phase change RAM (PRAM) and magnetoresistive RAM (MRAM) will revolutionize the storage system design. By introducing SCM into the solid-state drive (SSD), hybrid SCM/3D-NAND flash SSD and all SCM SSD achieve much higher write performance than all 3D-NAND flash SSD due to SCM’s fast speed. In addition, the performance of the SSD is workload dependent. Thus, it is meaningful to obtain the design guidelines of 3D NAND flash for both all 3D-NAND flash SSD and hybrid SCM/3D-NAND flash SSD with representative real-world workloads.

With ultra-high storage density, low bit cost and better performance, vertical three-dimensional (3D) NAND flash memory turns to be the main storage stream in the market. However, in the viewpoint of reliability, 3D NAND flash memory are quite different from traditional its 2D counterpart considering the special structures and integration processes in 3D NAND. In this work, several fundamental reliability problems in 3D NAND memory cells are addressed, including the polycrystalline Si channel, carrier tunneling layer and the silicon nitride charge storage layer.

NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory. Recently, 3-dimensional (3D) NAND flash memory was developed and started mass-production for reducing bit cost. By using 3D NAND flash memory, an advanced SSD has been intensively developed for high performance, and low power consumption, namely ecological environment. In this paper, NAND Flash memory technologies are discussed in the past, present and future.

Solid-state drives (SSDs) have a growing trend of replacing hard disk drives (HDDs) in large computing systems to meet the requirements of power and space. Data in SSD are stored in NAND flash memory cells. Since 2-dimensional (2D) scaling is facing various limitations, 3D-NAND flash memory architectures have been proposed to maintain the trend of bit density increase and bit cost reduction, which prefers large block sizes and page sizes. However, overly large block and page sizes flash memory harm the throughput of NAND flash devices. The actual page size and block size of the NAND flash memory product are as small as 8KB and 2MB respectively to avoid the performance degradation. Alternatively, emerging nonvolatile memory devices named storage class memories (SCMs) feature in high speed, low power consumption and high endurance. By combining SCM, large block sizes and page sizes, required especially for the 3D-NAND flash device case, are acceptable for SCM/NAND flash hybrid SSD. In this paper, a workload-aware NAND organization design is investigated for enhancing the performance of both SSD with only NAND flash memory and SCM/NAND flash hybrid SSD. From the experimental results, a 16MB NAND block size that corresponds to 512 layers and 16KB page size in a 512Gbit P-BiCS 3D-NAND flash memory can be acceptable for applications like relational database and financial online transaction processing. Additionally, a large NAND flash page size of 512KB is also acceptable for the firewall/web proxy, relational database and project directories applications. With SCM, the acceptable page and block sizes of the 3D-NAND flash memory can be magnified up to 64-times and 4-times, respectively, compared with the conventional SSD composed of only NAND flash memory.

This letter examined the natural local self-boosting effect of an inhibited channel in three-dimensional (3D) NAND flash memory. The inhibited channel in the 3D NAND flash structure can be in the floating state easily, because its channel is not connected directly to its substrate. Despite the application of the global self-boosted program-inhibit scheme, the selected wordline cell is localized automatically during the program pulse application. This phenomenon is analyzed using a computer-aided design simulation, and an analytical model of boosted potential of an inhibited channel in 3D NAND flash memory is proposed.

The shift of the threshold voltage distribution in 3D (three dimensional) NAND flash memory can lead to the overlapping of adjacent states, and subsequently read error. By merely adopting the default value provided by the manufacturer, the read offset in the controller could not keep low raw bit error rate (RBER) in the retention process. In this paper, we have developed a read offset model based on the dimensions of word-line (WL) and the shift of retention variations. Through mining the offline data, this new model can adjust to a more suitable read offset during retention variations. We have further proposed three different kinds of read voltage management strategies. Our experiment results show that this new model can optimize the read offset value and reduce the RBER effectively compared to the default setting provided by the manufacturer, and thus improve the reliability and performance of flash memory.

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell. Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

In order to keep reducing the bit cost, NAND Flash memory vendors have changed the NAND Flash technology from 2D to 3D since 2014. Moreover, 3D NAND Flash is becoming the mainstream of the NAND Flash based storage system from 2017. Owing to the storage material of NAND Flash changing from heavy doped poly-silicon to silicon-nitride, the inter-cell interference is ignored during programming operation to increase the write performance on 3D NAND Flash memory. However, in order to reduce the aspect ratio of the memory hole, the thickness of the inter word-line dielectric is reduced with the increasing of the stacking number. Accordingly, the Vth distribution is widened by the interference between the electrons in the silicon-nitride and the conductive channel between memory cells. This paper provides the measurement results of the cell-to-cell interference with the mass-produced 3D NAND Flash memory and proposes a method to reduce the cell-to-cell interference on 3D NAND Flash. Furthermore, the error bit of the 3D NAND Flash memory is 15% reduced and the endurance is 3X increased by the proposed method.

Three-dimension (3D) NAND flash memory is the preferred storage component of solid-state drive (SSD) for its high ratio of capacity and cost. Optimizing the reliability of modern SSD needs to test and collect a large amount of real-world error data from 3D NAND flash memory. However, the test costs have surged dozens of times as its capacity increases. It's imperative to reduce the costs of testing denser and high-capacity flash memory. To facilitate it, in this paper, we aim to enable reproducing error data efficiently for 3D NAND flash memory. We use a conditional generative adversarial network (cGAN) to learn the error distribution with multiple interferences and generate diverse error data comparable to the real-world. Evaluation results demonstrate it is feasible and efficient for error generation with cGAN.

Read Disturbs (RD) is a key reliability issue for NAND flash memory applications in hot storages. In traditional 2D NAND flash memory, RD caused error bits originate from the leakage currents via the tunneling oxide, which degrades when the cells suffer from repeated Program/Erase (P/E) cycling. In vertical 3D NAND flash memory, RD properties are quite different from its 2D counterpart, showing different dependences on read numbers, P/E cycling and even the data retention (DR) time. In this report, the underlying physical mechanism are investigated on the basis of comprehensive characterizations of triple-level-cell (TLC) 3D charge-trap (CT) NAND flash memory chips. Furthermore, several approaches will be introduced to suppress RDs in 3D NAND flash, showing that part of error bits from RD can be effectively recovered by optimizing the operation schemes. These results are important for robust reliability designs of NAND-based hot storage applications. (Acknowledgments: This work is supported by China Key Research and Development Program #2016YFA0201802, and the National Natural Science Foundation of China #61874068).

NAND flash memory density continues to scale to keep up with the increasing storage demands of data-intensive applications. Unfortunately, as a result of this scaling, the lifetime of NAND flash memory has been decreasing. Each cell in NAND flash memory can endure only a limited number of writes, due to the damage caused by each program and erase operation on the cell. This damage can be partially repaired on its own during the idle time between program or erase operations (known as the dwell time), via a phenomenon known as the self-recovery effect. Prior works study the self-recovery effect for planar (i.e., 2D) NAND flash memory, and propose to exploit it to improve flash lifetime, by applying high temperature to accelerate self-recovery. However, these findings may not be directly applicable to 3D NAND flash memory, due to significant changes in the design and manufacturing process that are required to enable practical 3D stacking for NAND flash memory. In this paper, we perform the first detailed experimental characterization of the effects of self-recovery and temperature on real, state-of-the-art 3D NAND flash memory devices. We show that these effects influence two major factors of NAND flash memory reliability: (1) retention loss speed (i.e., the speed at which a flash cell leaks charge), and (2) program variation (i.e., the difference in programming speed across flash cells). We find that self-recovery and temperature affect 3D NAND flash memory quite differently than they affect planar NAND flash memory, rendering prior models of self-recovery and temperature ineffective for 3D NAND flash memory. Using our characterization results, we develop a new model for 3D NAND flash memory reliability, which predicts how retention, wearout, self-recovery, and temperature affect raw bit error rates and cell threshold voltages. We show that our model is accurate, with an error of only 4.9%. Based on our experimental findings and our model, we propose HeatWatch, a new mechanism to improve 3D NAND flash memory reliability. The key idea of HeatWatch is to optimize the read reference voltage, i.e., the voltage applied to the cell during a read operation, by adapting it to the dwell time of the workload and the current operating temperature. HeatWatch (1) efficiently tracks flash memory temperature and dwell time online, (2) sends this information to our reliability model to predict the current voltages of flash cells, and (3) predicts the optimal read reference voltage based on the current cell voltages. Our detailed experimental evaluations show that HeatWatch improves flash lifetime by 3.85× over a baseline that uses a fixed read reference voltage, averaged across 28 real storage workload traces, and comes within 0.9% of the lifetime of an ideal read reference voltage selection mechanism.

Data-retention characteristics of 3-dimensional (3D) NAND flash memory have been evaluated with the optimal Vref (read reference voltage) shift in comparison with 2-dimentional (2D) (1Xnm) NAND flash memory. Bit-error rate (BER) of data-retention and write/erase (W/E) cycling in 3D NAND flash are much smaller than that in 2D NAND flash. Also, in 3D NAND flash, BER of Bottom Word-line is 1.9-times higher than Top Word-line, due to wider Vth distribution width. The data-retention lifetime of 3D NAND flash is estimated to about 10 years at 85degC, W/E=1~300 cycles by the Vth distribution margin evaluation without considering the inter-block, inter-wafer and inter-lot variations and process/voltage/temperature (PVT) variations of the read reference voltage circuit. On the other hand, the data-retention lifetime of 2D NAND flash is estimated 1000 years in W/E=1 and is rapidly degraded to 1 year in W/E=300. Therefore, 3D NAND flash is suitable to apply to Cold Flash with a few hundred times update and data center SSD with many times update. 2D NAND flash is suitable for digital archive: millennium memory with only one time write.