Solder Bump Joints Research Articles

Thermal Fatigue Reliability Assessment for Solder Bump Joint of BGA.

The authors have proposed the estimating method of thermal fatigue reliability for solder joints of electronic package, using the total equivalent inelastic strain range Δein and Manson-Coffin's law. However, as it is difficult to calculate it in the case of huge models, it is needed to establish a simple calculation method of Δein. In this study, the authors proposed a simple approach of FEM analysis for calculation of Δein. Approximate formula for relative displacements of solder joint using the results of the elastic analysis was examined in order to simplify huge inelastic analysis. In addition, using Statistical Design Support System (SDSS), they made the equation of inelastic strain range in the solder joints. And proposed simple estimation method of thermal fatigue life.

DESIGN AND MANUFACTURING OF MICRO VIA-IN-PAD SUBSTRATES FOR SOLDER BUMPED FLIP CHIP APPLICATIONS

A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint.

Applications of FEM for multiple laminated structure in electronic packaging

A special finite-element method for multiple laminated structure, previously proposed by the authors, is presented here. It can provide attractive results without three-dimensional finite-element discretization and can be applied to electronic packaging problems. The thermal stress analysis of the basic IC model, the practical IC model with lead fingers and the electronic printed board with solder bump joints are selected as the problems to deal with, and analyzed in detail. From the results of the basic IC model, the influences of varying chip size and package thickness for the stress distributions, are presented. The causes of failure for the real IC device are presented from the results of the practical IC model. In addition, influences of the solder joint arrangements for the thermal stresses are presented from the results of the electronic printed board with solder bump joints.

Thermal stability of various ball-limited-metal systems under solder bumps

Describes the thermal stability of ball-limited-metal (BLM) layers formed under controlled-collapse solder (lead-5 wt.% tin) bumps for flip-chip interconnections. All BLM systems used here consist of a triple-layer deposit of Cr or Ti as an adhesive, Ni, Mo, Pd, or Pt as a barrier, and Au as a surface metal. Using test chips with these BLM systems, mechanical pull-strength values of solder-bump joints are obtained. These values are associated with thermal phenomena at the interface between the BLM and solder layers. The chips with Ti adhesive layers show generally superior solder-joint strength to those with Cr layers, irrespective of the barrier metal used. This is due to the presence of a joint fracture mode closely related to the kind of adhesive metal. Among the BLM systems examined, Ti/Ni/Au is found to provide the most reliable solder joints. This is successfully utilized as a BLM system for GaAs devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reliability of flip chip solder bump joints : V. K. Nagesh. Proc. IEEE Reliab. Phys. Symp., 6 (1982)

Reliability of flip chip solder bump joints : V. K. Nagesh. Proc. IEEE Reliab. Phys. Symp., 6 (1982)