SOI PMOS Devices Research Articles

Influence of channel length on PD SOI PMOS devices under total dose irradiation

This paper mainly investigates the total dose irradiation effects on 0.8 μm PD SOI PMOS devices which are exposed to 60Co γ-rays at a dose rate of 50 rad(Si)/s. The channel length dependence of SOI PMOS devices at total dose irradiation is investigated. The result shows that the threshold voltage shift is only a little larger for shorter channel devices at the same total dose. However, the degradation of maximum transconductance for shorter channel devices is more significant. We found that the oxide-trapped charge is the main factor impacting the threshold drift. We may conclude that a short channel device can produce more interface trapped charges by using the subthreshold separation technology.

The 1/f Noise Performance for TFTs Fabricated in Three TFT Technologies: Monocrystalline Silicon on Glass, Low Temperature Polysilicon on Glass, and Silicon on Insulator

The 1/f noise characteristics were measured for CMOS devices fabricated in three different process technologies: conventional SOI (SmartCut), monocrystalline silicon on glass (SiOG) and low temperature polysilicon (LTPS). Noise slope and bias current parameters, from the SPICE2 low frequency noise model, were extracted from the 1/f measurements. The SPICE2 noise coefficient parameter, Kf, was extracted for each device. SOI PMOS (which exhibit the least amount of 1/f noise) establish a baseline noise level to compare TFT technologies against. SiOG and LTPS PMOS devices exhibit noise coefficients that were 1.89 and 2.93 times larger than the SOI PMOS device, respectively. The degraded 1/f performance of SiOG and LTPS devices when compared to SOI can be linked to the silicon-silicon dioxide interface trap density. All devices exhibited similar 1/f noise slopes, between 0.8 and 0.98, where processing variations were found to correspond to low slope values.

Analysis of current conduction in short-channel accumulation-mode SOI PMOS devices

This paper reports a compact analytical current conduction model for short-channel accumulation-mode SOI PMOS devices. Based on the study, the current conduction mechanism in a short-channel accumulation-mode SOI PMOS device is different from that in a long-channel one. As verified by the experimental data, the compact analytical model considering channel length modulation and prepinchoff velocity saturation gives an accurate prediction of the drain current characteristics.

Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices.

TCAD-based simulation of hot-carrier degradation in p-channel mosfets using silicon energy-balance and oxide carrier-transport equations

We present a TCAD-based approach for characterizing hot-carrier degradation in p-channel MOSFETs that includes models for hot-electron injection, carrier transport, and electron trapping in the oxide. The energy-balance equations have been solved in the silicon substrate to accurately model the carrier-heating and injection processes. This approach clearly illustrates the physical mechanisms responsible for hot-carrier degradation in p-channel MOSFETs. The simulations have been compared with experimental data obtained from 0.8μm SOI pMOS devices and show an excellent match.

Short-channel effect on the threshold voltage of accumulation-type, inversion-type and intrinsic-type SOI PMOS devices

Short-channel effect on the threshold voltage of accumulation-type, inversion-type and intrinsic-type SOI PMOS devices

An analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating at 77 K

This paper presents a closed-form analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating in the “delayed-turn-on” regime at liquid nitrogen temperature. As verified by the low-temperature PISCES results [Kuo et al., IEEE Trans. Electron Devices 39, 348–355 (1992)], the closed-form analytical delayed-turn-on model provides a good explanation of the delayed-turn-on behavior.

Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device

This paper reports on a simulation study on the back gate bias effect on the subthreshold behavior of a SiGe-channel SOI PMOS device using a device simulator. With a SiGe channel, the SOI PMOS device shows a smaller back gate bias effect as compared to the one without it.

An analytical back gate bias dependent threshold voltage model for SiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature

A unique delayed-turn-on phenomenon in an accumulation type SOI pMOS device operating at 77 K based on the low-temperature PISCES simulation is reported. As compared with the 300 K case, in the delayed-turn-on region, the accumulation-type SOI pMOS device at 77 K may not provide a larger transconductance as a result of the carrier freezeout effects in the thin film.