SOI CMOS Technology Research Articles

A Ka-band 27.6-dBm power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology

This paper presents a Ka-band power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology. The amplifier employs a quad-branch topology based on zero-degree power combiners/splitters, with each branch comprising two differential stages, each containing four stacked FETs. With a compression-state large-signal matching approach, this design achieves the saturated output power (Psat) of 27.6 dBm with 14.1 % peak power added efficiency (PAE), output 1-dB compression point (OP1dB) of 20.1 dBm at 35 GHz, according to electromagnetic simulation (EM) results. Additionally, it exhibits a peak gain of 39.2 dB at 33 GHz and a 3-dB bandwidth across 32–38 GHz. Offering a low-cost solution suitable for phased array radars and satellite communications.

SpacePix3: SOI MAPS detector for space radiation monitoring

The SpacePix3 monolithic active pixel sensor is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The detector is capable of detecting and differentiating protons, electrons, and heavy ions. Its active sensor area is 3.84×3.84 mm2, pixel matrix is arranged in a 64×64 square array with 60 µm pitch. The pixel front-end amplifier signal range is 1–80 ke-, extended up to 30 Me- using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at -150 V, creating a depleted layer approximately 35 µm deep. Impinging particle generates a charge pulse converted to a voltage pulse by the charge-sensitive amplifier. Maximum voltage memorized by the peak detector hold circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total current consumption is 31 mA from a 1.8 V power supply in the SPI mode.

A sub‐6GHz wideband low noise amplifier with high gain and low noise figure in 110‐nm SOI CMOS

AbstractThis letter presents a sub‐6 GHz wideband low noise amplifier (LNA) based on a double L‐type load network and utilizes the negative feedback technique. Using the cascode structure, along with the aforementioned techniques, it is possible to achieve a single‐stage wideband LNA with high gain and low noise figure (NF). Fabricated in 110‐nm SOI CMOS technology, the proposed LNA achieves a maximum power gain of 15.2 dB, noise figure of 1.0–1.56 dB. The 3‐dB bandwidth ranges from 3.05 to 4.55 GHz. The minimum power input at 1 dB compression point (IP1dB) is −17.1 dBm. The LNA area is 0.18 mm2 and dissipates a total power of 11.5 mW from a 1.4‐V power supply.

SpacePix2: SOI MAPS detector for space radiation monitoring

The SpacePix2 monolithic active pixel sensor (MAPS) is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The active sensor area is 3.84 × 3.84 mm2, pixel matrix is arranged as a 64 × 64 array with 60 µm pitch. The pixel front-end amplifier signal range is 2–80 ke−, extended up to 30 Me− using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at −150 V. Impinging particle generates a charge pulse converted to voltage pulse by charge sensitive amplifier (CSA). Maximum voltage memorized by the peak detector hold (PDH) circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total power consumption is 43 mA from a 1.8 V power supply. The ASIC has been tested in space in low Earth orbit (LEO) and sample data are shown.

An Ultra-Low-Power Octave-Tuning VCO IC With a Single Analog Voltage-Controlled Novel Varactor

In this paper, an ultra-low-power octave-tuning voltage-controlled oscillator (VCO) integrated circuit (IC) is proposed, using a novel varactor with a single control voltage. The novel varactor including VCO-gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K} _{\mathrm{ VCO}}$ </tex-math></inline-formula> ) improving structure consists of two parallel-connected inversion-mode MOS (I-MOS) -based varactors with shifted bias and an NMOSFET operating as a variable resistor. This novel varactor is able to give a large capacitance variation with a single analog control voltage. The proposed wideband VCO IC implementing this novel varactor is designed, fabricated, and evaluated fully on-wafer in 40-nm CMOS SOI technology. The proposed wideband VCO IC has exhibited a completely continuous measured tuning range (TR) of 67.9% from 3.2 to 6.49 GHz. The measured dc power consumption is from 0.35 to 1.36 mW throughout the whole TR under a supply voltage of 0.36 V. This is an extremely low dc power consumption among the reported sub-10-GHz octave-tuning VCO ICs so far. The measured peak figure-of-merit including TR (FoMT) of the proposed VCO IC is 210.4 dBc/Hz with a carrier frequency of 6.49 GHz.

An Integrated Primary Impulse Radio Ultra-Wideband Radar for Short-Range Real-Time Localization

This paper presents a primary impulse-radio ultra-wideband (IR-UWB) radar system for real-time short-range localization, e.g., for smart traffic and automotive applications. The radar system consisting of an integrated radar transceiver (TRx) using 45-nm SOI CMOS technology and an FPGA-based signal processing. The efficient transmitter (Tx), which complies with the regulations for both indoor and outdoor applications, modulates and emits a seventh derivative Gaussian pulse. In the receiver (Rx), echo signals will be amplified and sampled in real-time. The echo pulses are recovered by signal processing hardware on the FPGA, which is also used to perform simple classification tasks like user warning. The radar system is compact, portable, and power efficient. The Tx has a high-energy efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {11~ \text {p} \text {J} /pulse}$ </tex-math></inline-formula> . The proposed radar system achieves very high signal-to-noise ratio (SNR) and range precision. It has a maximum detection range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {15~m }$ </tex-math></inline-formula> and a range resolution down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {3~ \text {cm}}$ </tex-math></inline-formula> . Moreover, a target of interest can be warned with a latency as fast as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {16~\mu s }$ </tex-math></inline-formula> by using 1-bit real-time sampling.

A Monolithically Integrated Microcantilever Aptasensor Based on Partially Depleted Soi Cmos Technology

A Monolithically Integrated Microcantilever Aptasensor Based on Partially Depleted Soi Cmos Technology

Input-resistance reduced gm-boosted common-gate transimpedance amplifier for 100 Gb/s optical communication

This paper proposes a transimpedance amplifier (TIA) for a 100 Gb/s optical receiver. The proposed TIA adopts a gm-boosted common-gate input stage with a diode-connected transistor, which lowers the input resistance resulting in a high input pole frequency. It was designed and fabricated in 32 nm CMOS SOI technology. Measurement results indicate that the TIA achieves a bandwidth of 74 GHz and a transimpedance gain of 26 dBΩ while dissipating 16.5 mW under 1.5 V supply voltage. The bandwidth of the proposed TIA is larger by 48% or more when compared with state-of-the art TIAs.

Design of a K-Band High-Efficiency Power Amplifier in 45 nm SOI CMOS Technology

This paper presents a high efficiency K-band CMOS power amplifier (PA) in GlobalFoundries (GF) 45 nm SOI CMOS technology for 5 G applications. Compared with an ordinary two-stage PA, the PA uses a current-reused technique to enhance the power gain and efficiency within the frequency band. The resistance feedback structure of the power output stage improves the gain flatness and the output bandwidth, and reduces the matching components. The simulation results show that the output power (Pout) is more than 21.6 dBm from 18 to 27 GHz, while the small signal gain (S21) is more than 30.6 dB, the output 1 dB compression point (OP1dB) is 19.8 dBm and power-added efficiency (PAE) is 36.8%. With a 64-QAM LTE signal with 20-MHz bandwidth, adjacent channel leakage ratio (ACLR) is −31.2 dBc and the error vector amplitude(EVM) is less than − 26.7 dB at an average output power of 10.9 dBm. The chip area with pads is 0.75mm2, and consumes 15.1 mW from 2.4 V.

Design and process features of CMOS SOI transistors with increased tolerance to the total dose

The paper considers methods to improve integrated circuits’ tolerance based on the SOI CMOS technology to total dose radiation. The main effects that occur in SOI CMOS transistors as a result of radiation response with the VLSI are discussed. The final part of the work demonstrated the main methods that make it possible to increase the radiation hardness of ICs based on the SOI CMOS technology. The advantages and disadvantages of each technique will be discussed. The prospects for developing microelectronics products with increased tolerance to external influences will be analyzed under constant process node scaling.

Large-area femtosecond laser milling of silicon employing trench analysis

A femtosecond laser is a powerful tool for micromachining of silicon. In this work, large-area laser ablation of crystalline silicon is comprehensively studied using a laser source of pulse width 300 fs at two wavelengths of 343 nm and 1030 nm. We develop a unique approach to gain insight into the laser milling process by means of detailed analysis of trenches. Laser scribed trenches and milled areas are characterized using optical profilometry to extract dimensional and roughness parameters with accuracy and repeatability. In a first step, multiple measures of the trench including the average depth, the volume of recast material, the average longitudinal profile roughness, the inner trench width and the volume removal rate are studied. This allows for delineation of ablation regimes and associated characteristics allowing to determine the impact of fluence and repetition rate on laser milling. In a second step, additional factors of debris formation and material redeposition that come into play during laser milling are further elucidated. These results are utilized for processing large-area (up to few mm2) with milling depths up to 200 µm to enable the fabrication of cavities with low surface roughness at high removal rates of up to 6.9 µm3 µs−1. Finally, laser processing in combination with XeF2 etching is applied on SOI-CMOS technology in the fabrication of radio-frequency (RF) functions standing on suspended membranes. Performance is considerably improved on different functions like RF switch (23 dB improvement in 2nd harmonic), inductors (near doubling of Q-factor) and LNA (noise figure improvement of 0.1 dB) demonstrating the applicability of milling to radio-frequency applications.

ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 upmu m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5times higher performance and 2.4times higher computational energy efficiency at a 1.6times larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

Fully Differential Ultra-Wideband Amplifier With 46 −dB Gain and Positive Feedback for Increased Bandwidth

This brief reports a three-stage fully differential UWB amplifier with high and flat gain. It is proposed to be applied in the receiver part of a primary IR-UWB radar that is designed for real-time pedestrian localization. The amplifier was fabricated using 45 nm SOI CMOS technology and has been measured on a probe station and was demonstrated on a PCB. A differential cascode structure with positive feedback is employed and offers 45.8±0.5 dB gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) with a -3 dB bandwidth from 3.1 GHz to 10.6 GHz. The amplifier also achieves a wideband and flat input impedance matching with return loss smaller than -10 dB. The measured minimum noise figure is about 4 dB. The output power at 1 dB compression point is 10.2 dBm at 7 GHz. The amplifier occupies an active chip area of 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 125 mW from a 1.5 V supply. To the best knowledge of the authors, the proposed amplifier provides the highest gain and the best FOM in this frequency band in comparison with other designs that have been reported to date.

Coherent Radiation From a Swarm of Wirelessly Powered and Synchronized Sensor Nodes

This paper presents a novel technique to synchronize a swarm of sensor nodes at the RF domain and produce coherent radiation from the sensor nodes to increase the amplitude of the reflected signal. A network is formed by an array of microchips that are wirelessly powered, and upon activation, radiate back an RF signal. The phase of the radiated signals from each microchip is synchronized using a wireless reference signal. This technique results in a coherent amplitude combing and power amplification. The microchips are fabricated in a 180-nm CMOS SOI technology. Each microchip occupies a total area of $3.9\times 0.7\,\,\textit {mm}^{2}$ that includes three on-chip dipole antennas that are used for power delivery, injection locking, and back RF reflection. Measurement results reveal that a reference signal in a frequency range of 7.72-7.79 GHz can successfully synchronize the reflected signals radiated from the microchips through a sub-harmonic injection locking scheme. A wireless reference signal of 7.733 GHz synchronizes an array of $2\times2$ microchips. The microchips are locked to half of the reference frequency and produce coherent radiation at 3.866 GHz. This scheme results in a power elevation of ~12 dB on the reader side.

Millimeter-wave Frequency Reconfigurable Low Noise Amplifiers for 5G

In this brief, designs of two millimeter wave (mmWave) reconfigurable multi band low noise amplifiers (LNA) are presented targeted for fifth generation (5G) communications. A reconfigurable tunable load based on electrical and magnetic tuning is proposed to cover three mmWave frequency bands for 5G, i.e., 24 GHz, 28 GHz and 39 GHz. Two LNA structures are designed and fabricated using 45nm CMOS SOI technology. The first toplogy (LNA1) is composed of a single input wideband matching circuit to cover frequency operations from 24 GHz to 40 GHz. On the other hand, second topology (LNA2) uses three separate narrowband match inputs, one for each frequency band, with combined output. Design methodology of passive and active devices is presented towards compact integration of LNAs for systems such as, phased arrays. Ground plane and its impact on the performance parameters is also discussed in this brief. Measurement results show a wideband noise figure (NF) ranging from 3.8 dB to 4.9 dB and gain of 8.5 dB to 12.5 dB for LNA1 at different bands. Similarly, LNA2 exhibits NF of 4.5 dB to 5.5 dB and gain of 9.5 dB to 15.5 dB across all bands. Total area (including pads) of LNA1 and LNA2 are 0.316 mm2 and 0.695 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

Tunable 0.7–2.8-GHz Reflection-Mode N-Path Filters in 45-nm SOI CMOS

This article presents the principles of operation of a reflection-mode $N$ -path filter and then discusses both single-balanced and double-balanced implementations. The single-balanced approach can be used to realize tunable filters with extremely low insertion loss; however, the circuit also exhibits harmonic responses. The double-balanced reflector naturally rejects even-order harmonics and can be modified to cancel the third harmonics as well to provide a tunable $N$ -path filter with the second through fourth harmonics rejected. This comes at the expense of increased insertion loss to support the required balun circuitry used to balance the mixers. Prototypes for both types of filters have been realized in the 45-nm SOI CMOS technology. Measurements on the single-balanced reflection-mode filter indicate 0.8–2.4-dB insertion loss across a 700–3000-MHz tuning range. The input-referred 1-dB compression point is 0 dBm and the input-referred third-order intercept point (IIP3) is +10-dBm in-band and +22-dBm out-of-band (OOB), and the circuit consumes 2.5–7.2 mW of power. Measurements on the double-balanced reflection-mode filter indicate 1.9–4.4-dB insertion loss across a 700–2800-MHz tuning range. The input-referred 1-dB compression point is +0.75 dBm, and IIP3 is >+16.3-dBm in-band and >+19.5-dBm OOB, and the circuit consumes a total of 4.0–15.6 mW of power.

A Low-Power, High-Linearity Wideband 3.25 GS/s Fourth-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers

This article presents a 3.25 GS/s fourth-order programmable analog finite impulse response (AFIR) filter for flexible discrete time analog signal processing (DT-ASP). For wide application of the proposed AFIR filter, it is designed for full bandwidth utilization up to the Nyquist rate, programmable via the multiplier coefficient set. In this implementation of the FIR function, split-capacitive DACs (split CDACs) are adopted as coefficient multipliers, providing high-linearity over the full frequency range and low power consumption. Individual coefficients are digitally controlled with total 7-bit codes, consisting of 6-bit fractional value, and 1-bit for sign selection. The addition is simply implemented in the current-domain. Noise and effects of the time-interleaved operation are analyzed to understand limitations on the dynamic range. The proposed AFIR filter is implemented in 32-nm SOI CMOS technology; the core area of the circuit is 0.1 mm2. Measurement results demonstrate transfer function configurability over all possible low pass filter (LPF), bandpass filter (BPF), and high pass filter (HPF) linear phase coefficient sets. The AFIR filter achieves > 11-dBm third-order input intercept point (IIP3) over the full frequency range with a 0.9-V supply. The maximum power consumption is 10.6 mW.

An Efficient Ultrawideband Pulse Transmitter With Automatic On–Off Functionality for Primary Radar Systems

This letter proposes an ultrawideband (UWB) transmitter for a UWB primary impulse radar that is designed for real-time pedestrian localization. The proposed transmitter applies a novel combination of a UWB pulse generator followed by a UWB amplifier to boost output pulse amplitude, which is able to be turned off automatically after one pulse transmission in order to reduce power consumption. The transmitter has been fabricated using 45-nm SOI CMOS technology and has been measured on a printed circuit board (PCB). The produced pulses possess a high measured peak-to-peak amplitude of 425 mV and a width of around 600 ps. The power spectral density (PSD) of the pulse achieves a maximum of −41 dBm/MHz at 6 GHz with a −10-dB bandwidth of 4.5 GHz from 3.3 to 7.8 GHz that assures that the proposed transmitter complies with the regulation of the U.S. Federal Communications Commission (FCC) for UWB outdoor applications. The pulse generator consumes around 10 pJ/pulse from a 1-V supply, which is very low among the similar designs, and remains almost constant with an increasing pulse repetition time (PRT).

RADIATION RESISTANT BIPOLAR SOI TRANSISTORS

In this paper the new design of lateral bipolar transistors is presented, made on the basis of the charge carrier transport modeling. New design provides high level of base current transmission coefficient and enhanced radiation resistance. The manufacturing technology of the lateral bipolar transistors is compatible with a submicron SOI CMOS technology and can be of vital importance when developing RF analogue-to-digital microcircuits for ionizing radiation resistant satellite-navigation equipment.