SOI CMOS Technology Research Articles

High Temperature GaN Gate Driver in SOI CMOS Technology

Abstract Power electronics is a rapidly developing application area for high temperature electronics. Wide bandgap semiconductors have intrinsic advantages for high temperature operation due to the large bandgap in comparison to silicon based semiconductors. Especially GaN is a promising material for power semiconductors due to the possibility to process GaN on silicon carrier wafers, which results in lower device costs in comparison to SiC. In addition GaN provides higher switching frequencies and lower on-resistances of power devices. In combination these advantages enable the design of high performing, small size power modules operating at elevated temperatures. However, in order to exploit all benefits from GaN technology, new approaches in driver design are necessary. In this work a GaN specific gate driver supporting increased switching frequency, low driver output resistance, and GaN specific control voltages is presented. The driver has been implemented in a 0.35 micron thin film SOI-CMOS technology allowing high temperature operation up to 250 °C. The driver output characteristic is digitally adjustable with configuration data stored in an on-chip non-volatile memory based on EEPROM.

HOT-300 – A Multidisciplinary Technology Approach Targeting Microelectronic Systems at 300 °C Operating Temperature

Abstract Several applications in the fields of industrial sensors and power electronics are creating a demand for high operating temperature of 300 °C or even higher. Due to the increased temperature range new potential defect risks and material interactions have to be considered. As a consequence, innovation in semiconductor, devices and packaging technologies has to be accompanied by dedicated research of the reliability properties. Therefore various investigations on realizing high temperature capable electronic systems have shown that a multidisciplinary approach is necessary to achieve highly reliable solutions. In the course of the multi-institute Fraunhofer internal research program HOT-300 several aspects of microelectronic systems running up to 300 °C have been investigated like SOI-CMOS technology and circuits, silicon capacitor devices, a capacitive micromachined ultrasonic transducer (CMUT), ceramic substrates and different packaging and assembly techniques. A ceramic molded package has been developed. Die attach on different leadframe alloys were investigated using silver sintering and transient liquid phase bonding (TLPB). Copper and gold wire bonding was studied and used to connect the chips with the package terminals. Investigations in flip chip technology were performed using Au/Sn and Cu/Sn solder bumps for transient liquid phase bonding. High operating temperatures result in new temperature driven mechanisms of degradation and material interactions. It is quite possible that the thermomechanical reliability is a limiting factor for the technology to be developed. Therefore investigations on material diagnostics, reliability testing and modeling have been included in the project, complementing the technology developments.

A high‐power, broadband 245–285 GHz balanced frequency doubler in 45 nm SOI CMOS

ABSTRACTA compact, broadband balanced frequency doubler that achieves state‐of‐the‐art output power with a usable bandwidth of over 40 GHz (245–285 GHz) has been presented. This wide bandwidth is twice that of previously published CMOS doublers from 140 to 340 GHz, enabling emerging applications in wide bandwidth communication and radar at sub‐THz frequencies. The doubler is designed and fabricated in a 45 nm SOI CMOS technology with an effective area of only 0.12 mm2. The frequency doubler exhibits −15 ± 1.5 dB conversion loss over 40 GHz bandwidth and can provide as high as 200 μW power while consuming 19 ± 1 mW dc power from a 1.1 V supply. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:423–426, 2016

An Investigation of the SET Response of Devices and Differential Pairs in a 32-nm SOI CMOS Technology

The single event effect (SEE) response of devices and differential pairs in a 32-nm SOI CMOS technology is explored using laser-induced carrier injection and TCAD simulations. Both nFETs and pFETs in this technology exhibit similar sensitive area to laser-induced SEE and are strongly dependent on the drain bias condition. TCAD simulations were conducted in order to confirm results and utilize a 3-D mixed-mode simulation approach to more accurately model testing conditions. The differential pair (diff. pair) circuit SEE response extends the discussion to include the use of these devices in a core analog/RF circuit block. The analysis includes the use of floating body (FB) and body-connected (BC) devices. Body-connected FETs tend to exhibit a transient response that is much shorter in duration when compared directly to its floating body counterpart.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces.

High performance tunnel field-effect transistor by gate and source engineering

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high ION/IOFF ratio (∼107) at VDS = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼108 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec−1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Operation of thin-film gated SOI lateral PIN photodetectors with gate voltage applied and intrinsic length variation

This paper describes the operation principle of thin-film gated SOI lateral PIN photodetectors, and an analytical model of depletion voltage is presented and validated by two-dimensional Atlas simulations. With gate voltage applied to achieve fully depleted (FD) condition in intrinsic region, the variation of intrinsic length (Li) on photocurrent and dark current characteristics, sensitivity, and speed is addressed. With Li between 1 and 10μm, the simulated results predict internal quantum efficiency (QI) in excess of 95% even near 100% at a 400nm wavelength. Also, QI can yield over 87% for the long channels. Under FD condition, the total −3dB frequency value can achieve 16GHz (19GHz) for Li=1 and 4.1GHz (6.2GHz) for Li=2μm with VK=1.0V (2.0V). And a high ratio of more than 107 between illuminated and dark currents can be yielded for all detectors realized in 0.18μm SOI CMOS technology.

Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails

This paper presents Razor-Lite, which is a low-overhead register for use in error detection and correction (EDAC) systems. These systems are able to eliminate timing margins by using specialized registers to detect setup time violations. However, these EDAC registers incur significant area and energy overheads, which mitigates some the system benefits. Razor-Lite is a new EDAC register that addresses this issue by adding only 8 additional transistors to a conventional flip-flop design. The Razor-Lite flip-flop achieves low overhead via a charge-sharing technique that attaches to a standard flip-flop without modifying its design. Side-channels connected to the floating nodes generate error flags through simple logic gates totaling 8 transistors, enabling register energy/area overheads of 2.7%/33% over a conventional DFF, while also not incurring extra clock or datapath loading or delay. Razor-Lite is demonstrated in a 7-stage Alpha architecture processor in a 45nm SOI CMOS technology with a measured energy improvement of 83% while incurring a 4.4% core area overhead compared to a baseline design.

SOI Hall cells design selection using three-dimensional physical simulations

The main characteristics of Hall Effect Sensors, based on “silicon-on-insulator” (SOI) structure in the ideal design features, are evaluated by performing three-dimensional physical simulations. A particular Hall shape reproducing an XFAB SOI XI10 integration process is analyzed in details. In order to assess the performance of the considered Hall cell, the Hall voltage, absolute sensitivity and input resistance were extracted through simulations. Electrostatic potential distribution and Hall mobility were also produced through simulations for the considered SOI Hall Basic cell. A comparison between the performance of the same Hall cell manufactured in regular bulk and SOI CMOS technology respectively is given.

A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters

A mm-wave I-Q power-DAC is reported at $W$ -band. The circuit, which is fabricated in a 45 nm SOI CMOS technology, employs a series-stacked Gilbert-cell output stage with gate finger geometry segmentation to directly modulate a 85–95 GHz carrier. The Gilbert-cell provides phase inversion and 7 bits for ASK envelope modulation, each of which can be switched at speeds up to 15 Gb/s. A ninth bit turns the entire DAC cell on and off at 15 Gb/s, as needed to create an arbitrary 15 Gbaud QAM constellation in a symmetrical 4×4 I–Q power-DAC transmitter array, with free-space power combining and antenna-level segmentation. The measured output power and PAE of the I or Q DAC cells are 19 dBm and 8.9%, respectively. Three effective bits of amplitude resolution and one phase bit are estimated from the small-signal S-parameter measurements in the 80–95 GHz range. The envelope amplitude resolution reduces to only two effective bits under saturated output power operation. The OOK bit provides over 45 dB of measured attenuation and dynamic range, relative to the peak output power.

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved f<SUB>t</SUB>BV<SUB>CEO</SUB> product (397 GHzV). As the BV<SUB>CEO</SUB> value is higher for low value of epi layer doping, higher supply voltage can be used to increase the ft value of the HBT. At 1.8 V V<SUB>CE</SUB>, the f<SUB>t</SUB>BV<SUB>CEO</SUB> product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV f<SUB>t</SUB>BV<SUB>CEO</SUB> product at 1.2 V V<SUB>CE</SUB>). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

THz Measurements and Calibration Based on a Blackbody Source

This paper presents a low-cost measurement setup for THz applications, based on a blackbody source, which is a commercial off-the-shelf (COTS) component. This measurement approach resembles the natural operating conditions of passive imaging systems and hence is more adequate in the characterization of the operation of THz sensors and filters for passive systems than narrowband THz sources. The calibration methodology of mesh filters that may block the unwanted IR radiation as well as that of THz thermal sensors is discussed. The components for uncooled passive thermal imaging: the innovative CMOS-SOI-NEMS thermal sensor (the TeraMOS) as well as mesh filters are characterized in the measurement setup presented here. The TeraMOS sensor reported here is a small array of 4 ×4 pixels, each 100 ×100 (μm)2, with CMOS transistors with W/L=2/40, which are electrically connected but are thermally isolated. The NEP is of the order of NEP/√Hz|1 Hz=10 pW/√Hz, when viewing blackbodies at T=1300 K. The values of D* and NETD, obtained from this NEP, are 0.2·1010 cm√Hz/W and ~ 0.2 K. The corresponding NETD of a single pixel is ~ 0.8 K, indicating that this uncooled THz sensor in standard CMOS-SOI technology may enable monolithic uncooled passive THz imagers.

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer

We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz imaging for security and medical-diagnostic applications. The device is fabricated in a 180-nm CMOS SOI technology followed by a post-CMOS MEMS process which guaranties a very high thermal insulation of the sensor. In this sensor, the wide bandwidth THz antenna absorbing the electromagnetic field is directly coupled to the bolometer for maximum energy collection, whereas its design aims at minimizing its thermal mass as is necessary for fast frame rates. DC measurements before and after the MEMS process as well as sensor output signal time constant and THz antenna pattern measurements are presented. The final sensor is part of a large pixel array of 117 elements. Simulated array characteristic is presented proving that the mutual interaction between the pixels is small enough for imaging applications.

Evaluating the Effects of Single Event Transients in FET-Based Single-Pole Double-Throw RF Switches

The impact of single event transients (SETs) on single-pole double-throw (SPDT) RF switch circuits designed in a commercially-available, 180 nm second-generation SiGe BiCMOS (IBM 7HP) technology is investigated. The intended application for these SPDT RF switches requires a 1 GHz to 20 GHz band of operation, relatively low insertion loss (<; 3.0 dB at 20 GHz), and moderate isolation (> 15 dB at 20 GHz). Two-photon absorption experiment results reveal that the SPDT switches are vulnerable to SETs due to biasing effects as well as the triple-well (TW) nFETs, which are found to be more sensitive to SETs than bulk nFETs. From these results, potential implications are discussed and mitigation strategies are proposed. To verify one of the proposed mitigation techniques, SPDT switches were also designed in a 180 nm twin-well SOI CMOS (IBM 7RF-SOI) technology. A different biasing technique is implemented to help improve the SET response. The fabricated SOI SPDT switches achieve an insertion loss of <; 1.04 dB at 20 GHz and > 21 dB isolation at 20 GHz. For this circuit, no transients were observed even at very high laser energies (≈ 5 nJ).

RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.

Research on single-event transient mechanism in a novel SOI CMOS technology

Research on single-event transient mechanism in a novel SOI CMOS technology

A Wideband Power Amplifier in 45 nm CMOS SOI Technology for X Band Applications

A fully-integrated wideband power amplifier (PA) operating in 9-15 GHz range is implemented in a standard 45 nm CMOS SOI technology. The PA is designed with three dynamically-biased stacked Cascode cells (6 stacked transistors) to overcome the low breakdown voltages of nanoscale CMOS transistors. The stacked Cascode cells ensure stable operation and facilitate high gain, and high optimum load impedance, leading to high output power, high efficiency and good linearity characteristics over the entire bandwidth. The unbalanced amplitude and phase of drain-source voltage signals caused by internodal parasitic capacitance are equalized by adjusting the sizing of transistors. With a supply voltage of 4.8 V at 12 GHz, the measured saturated output power and linear power are 22.5 dBm and 19.2 dBm, respectively, while the peak power-added efficiency (PAE) is 19.2%. At a reduced power supply of 3.6 V, the PA achieves peak PAE of 25.7% where the drain efficiency reaches 40.7%. Including its pads, the PA occupies a compact chip area of 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .