Soft-output MIMO Detector Research Articles

Maximum Likelihood and Soft Input Soft Output MIMO Detection at a Reduced Complexity

This paper proposes an efficient pruning algorithm for MIMO detector, which not only achieves the same performance of the maximum likelihood (ML) decoder, but also massively reduces the number of visiting nodes. The proposed algorithm applies correct sorting order so that it achieves the same performance of the ML decoder. Thanks to the use of the correct ordering, both child and sibling nodes can be pruned efficiently. As a result, the number of visiting nodes is significantly reduced. To acquire properly sorted order, we propose fast sorting algorithms that generate the exact sorted sequence. Furthermore, the proposed schemes can be applied in SISO MIMO detector. The advantages of the proposed sphere decoder become more pronounced in high-order modulation schemes.

A 70 pJ/b configurable 64-QAM soft MIMO detector

An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed soft-output MIMO detector attains a peak coded data throughput of 2 Gbps. Furthermore, this detector is also suitable for low-power mobile applications that require high data rates, achieving a low decoding energy per bit of 70.3 pJ/bit at 1.1 V supply, while providing a data throughput of 640 Mbps in a 65 nm CMOS technology. The proposed design has the best throughput per unit area among all reported fabricated designs to-date.

A 4 <formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> 4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications

This paper presents the design and implementation of a 4 $\times$ 4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high-throughput wireless communication systems. The receiver uses bandwidths of 40, 80, and 160 MHz that correspond to three operation modes of 128, 256, and 512-point FFT, respectively. Four spatial streams are supported to offer the maximum uncoded data rate of 2.6 Gbps. Channel pre-processing based on sorted QR decomposition and the non-constant K-best soft-output MIMO detector are adopted to enhance the system performance. The addressing scheme for the QR phase memory is proposed to deal with the processing-time discrepancy between the write-in and read-out accesses. The high-throughput pipelined architecture for the non-constant K-best soft-output MIMO detector with selected discard-paths is analyzed to show a balance between performance and complexity. This receiver IC integrates 1.034 M logic gates as well as a total of 835 Kb SRAM in 90 nm CMOS technology and can generate hard output for 64-QAM constellation. The coded system performance is also provided with the soft-output MIMO detection. From the measurement results, the power consumption of the chip is 424 mW, 97 mW, and 26 mW at 1.16 V, 0.8 V and 0.66 V, respectively, for operations in 160 MHz, 80 MHz, and 40 MHz bandwidth modes. Compared to the prior works for 80 MHz channel bandwidth, this work supports wider channel bandwidth and achieves higher throughput.

An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection

Lattice Reduction aided MIMO detectors have been demonstrated to offer a promising gain by providing near-optimal performance. This paper presents a C-programmable ASIP baseband processor, for near-optimal MIMO detection targeting a 4?4 LTE system. The detector supports multiple MIMO detection modes, with both hard and soft output. In order to improve implementation efficiency, the previously reported MIMO detection algorithm Multi-Tree Selective Spanning Detector (MTSS) is modified to use orthogonal real-valued decomposition (ORVD). Afterwards, a low-complexity log-likelihood-ratio (LLR) improvement technique called counter-ML bit-flipping algorithm is proposed. The proposed LLR generation algorithm has been designed to take advantage of MTSS, by maximizing the reuse of computations. Performance of the proposed solution can be tuned ranging from SIC to near-ML to near-MAP. The baseband processor is designed using 40 nm process technology with an equivalent gate-count (GE) of 68.41 kGE. Operating at 600 MHz for a 4?4 QAM-64 LTE system, the processor delivers peak-throughputs of 3.6 Gbps and 2.05 Gbps in case of hard and soft output MIMO detection, with 13.03 mW and 22.99 mW respective power consumption. The corresponding energy efficiency is 3.61 pJ/bit and 11.17 pJ/bit. In terms of energy efficiency, the proposed reconfigurable solution is comparable to recently reported ASIC MIMO detectors, while providing multiple-modes of operation and the flexilibility of C-programming.

A low-latency high-throughput soft-output signal detector for spatial multiplexing MIMO systems

This paper presents a low latency, high throughput soft-output signal detector for a 4×4 64-QAM spatial-multiplexing MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a channel-adaptive node perturbation technique to generate a list of candidate vectors around an initial linear estimation. The detection algorithm provides a large range and convenient performance-complexity trade-off by adjusting the node perturbation parameter. A partial-parallel pipelined VLSI architecture is developed to implement the algorithm with high throughput, low processing latency, while offering the flexibility to support run-time performance tuning. Moreover, a fast and hardware-friendly node enumeration scheme is developed to further reduce the processing delay by exploiting the geometric property of the quadrature amplitude modulation (QAM) constellation. The detector was synthesized using Synopsys Design Compiler with a 65nm CMOS standard cell library. The core area is 0.58mm2 with 290K gates. The peak throughput is 3Gb/s at 500MHz clock frequency with a latency of 20ns. Compared to other reported soft-output MIMO detectors, this is a latency reduction of 71%. The corresponding energy consumption is 33pJ per bit detection.

Reduced Complexity Soft-Output MIMO Sphere Detectors—Part II: Architectural Optimizations

In Part I, we presented algorithmic optimizations for a soft-output (SO) tree-search MIMO detector targeted at reducing the node count complexity for a given error-rate performance. We present in this part the architecture for a hardware-efficient pipelined detector that incorporates all these optimizations. A detailed gate complexity analysis of the architecture is conducted, including arithmetic optimizations to minimize the use of multipliers for distance computations by exploiting the lattice structure, as well as efficient pointer logic for implementing child enumeration, internal node-pruning and node-skipping steps. For multitone OFDM symbol detection using multiple tree-search detectors, we propose an efficient scheduling scheme that exploits the slack in node count from tone-to-tone detection. By ordering the tones according to increasing order of their channel matrix orthogonality defect, the detector maximizes the slack of early terminating detectors and forwards it to ill-conditioned tones that require more detection time. Case studies and simulation experiments were conducted based on a 4-layer 64-QAM MIMO system for LTE. Simulations and VLSI synthesis results demonstrate that the proposed optimizations require a chip area of only 85 kGE to implement a 64-QAM SO MIMO detector for LTE capable of attaining almost ML performance with an SNR loss of only 0.85 dB.

Exploration of Lattice Reduction Aided Soft-Output MIMO Detection on a DLP/ILP Baseband Processor

Lattice Reduction aided soft output MIMO detectors (LR-SOMD) have been demonstrated to offer a promising gain. This work explores the potential of implementing a LR-SOMD on a parallel programmable baseband processor. In this paper, first a LR algorithm called the Data Regularized Parallel Lattice Reduction algorithm (DRP-LR) is proposed. Afterwards, a low-complexity LR-SOMD, Radius Constrained Multi-Tree Selective Spanning (RC-MTSS) is presented. RC-MTSS uses a novel multiple-tree search approach for LR-SOMD, while combining the benefits of Sphere Detection (SD) and Selective Spanning with Fast Enumeration (SSFE). A fixed complexity LR-SOMD, Multi-Tree Selective Spanning (MTSS) is also proposed for implementation. Both the algorithms, DRP-LR and MTSS, are enabled to exploit data level parallelism (DLP) and instruction level parallelism (ILP). In order to evaluate performance, the proposed DRP-LR and MTSS are implemented on the ADRES baseband processor for a 4 × 4 LTE system using QAM-64. DRP-LR achieves an average throughput of 33.33 M LR per second, which is comparable to recently reported ASIC implementations, while MTSS shows an average throughput of 730 Mbps on the same processor. To the best of authors' knowledge, this is the first reported implementation of a LR-SOMD algorithm on a parallel programmable baseband processor.

Approximating the LLR Distribution for a Class of Soft-Output MIMO Detectors

We present approximations of the LLR distribution for a class of fixed-complexity soft-output MIMO detectors, such as the optimal soft detector and the soft-output via partial marginalization detector. More specifically, in a MIMO AWGN setting, we approximate the LLR distribution conditioned on the transmitted signal and the channel matrix with a Gaussian mixture model (GMM). Our main results consist of an analytical expression of the GMM model (including the number of modes and their corresponding parameters) and a proof that, in the limit of high SNR, this LLR distribution converges in probability towards a unique Gaussian distribution.

Factor-Graph-Based Soft-Input Soft-Output Detection for Frequency-Selective MIMO Channels

In this letter we consider a MIMO communication system with iterative detection over a frequency-selective MIMO channel. We present a soft-input soft-output MIMO detector based on a cyclic factor graph representation and the sum-product algorithm with two different message schedules (serial and parallel). Computer simulations show that both schedules provide near-optimum performance in terms of bit error rate, while achieving a remarkable reduction in complexity compared to the optimal MAP detector.

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> of the trellis maps to a possible complex-valued symbol transmitted by antenna <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> . Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 × 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps.

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection

Multiple‐antenna systems are a promising approach to increase the data rate of wireless communication systems. One efficient possibility is spatial multiplexing of the transmitted symbols over several antennas. Many different MIMO detector algorithms exist for this spatial multiplexing. The major difference between different MIMO detectors is the resulting communications performance and implementation complexity, respectively. Particularly closed‐loop MIMO systems have attained a lot of attention in the last years. In a closed‐loop system, reliability information is fed back from the channel decoder to the MIMO detector. In this paper, we derive a basic framework to compare different soft‐input soft‐output MIMO detectors in open‐ and closed‐loop systems. Within this framework, we analyze a depth‐first sphere detector and a breadth‐first fixed effort detector for different application scenarios and their effects on area and energy efficiency on the whole system. We present all system components under open‐ and closed‐loop system aspects and determine the overall implementation cost for changing an open‐loop system in a closed‐loop system.

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO) detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

A 74.8 mW Soft-Output Detector IC for 8$\,\times\,$8 Spatial-Multiplexing MIMO Communications

In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 × 8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2 × 2 up to 8 × 8 and modulation order from QPSK to 64-QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input channel decoders and iterative decoding system. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and superior error rate performance, called modified best-first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-dual-heap (quad-DEAP) circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this chip is configured as 4 × 4 64-QAM and 8 × 8 64-QAM soft-output MIMO detectors, it achieves average throughputs of 431.8 Mbps and 428.8 Mbps with only 58.2 mW and 74.8 mW respective power consumption and reaches 10-5 coded bit error rate (BER) at signal-to-noise ratio (SNR) of 24.2 dB and 22.6 dB, respectively.