Abstract
In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 × 8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2 × 2 up to 8 × 8 and modulation order from QPSK to 64-QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input channel decoders and iterative decoding system. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and superior error rate performance, called modified best-first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-dual-heap (quad-DEAP) circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this chip is configured as 4 × 4 64-QAM and 8 × 8 64-QAM soft-output MIMO detectors, it achieves average throughputs of 431.8 Mbps and 428.8 Mbps with only 58.2 mW and 74.8 mW respective power consumption and reaches 10-5 coded bit error rate (BER) at signal-to-noise ratio (SNR) of 24.2 dB and 22.6 dB, respectively.
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