Smart Power ICs Research Articles

An on-chip integrated current sensor with high precision and large current range for smart power ICs

This work presents a precision current sensor with a high gain amplifier. Three aspects are improved. Firstly, the gain boosting is achieved by adding nested-amplifiers, namely AMPH and AMPL. Secondly, the DC error is eliminated by implementing a cascode current mirror branch with bias current compensation. Thirdly, the damage of large negative overshoot voltage to the operational amplifier is avoided because of the inserted switch transistors disconnecting the amplifier from load. For the ratio of main-FET to sense-FET, a factor of M = 5000 is chosen to keep the power consumption low. Measurement results show that this current sensor can operate from −60 °C to 120 °C with supply voltage from 10 V to 30 V. The measured absolute error between the sensed signal and the load current is less than 3% in range of 20 mA to 3.6 A at 27 °C. This current sensor has been fabricated in a 0.5 μ m SOI BCD process, which can be applied in smart power ICs.

Qualification extension of automotive smart power and digital ICs to harsh aerospace mission profiles: Gaps and opportunities

Historically the aerospace market has always chosen high level reliability solutions through customized technologies and processes, in order to cope with the requirement driven by mission profiles and application environment severity.In parallel, Automotive market required more and more high reliability targets. As a consequence, the qualification activity has evolved, passing from a stress driven approach strictly based on AEC-Q100 standard to a failure mode driven approach oriented to satisfy the robustness criteria required by TIER1 and Car Makers.Starting from this scenario, new market opportunities for Automotive devices can be identified, since the most reliable of them are today eligible to be sold to aerospace manufacturers with important cost saving thanks to massive production volumes of consolidated technologies.A gap may still persist and has to be carefully explored. First of all, a study of the different application constraints has to be carried out and the potential failure modes activated by Aerospace cold unbalanced mission profile, atmospheric pressure and radiations have to be analysed.Experimental evidences have been collected as first step on advanced CMOS technologies, and their extension to the smart-power families, where digital and power coexist together, will be shortly discussed in this paper.

Smart Power Devices and ICs Using GaAs and Wide and Extreme Bandgap Semiconductors

We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, and diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences.

Guest Editorial Special Issue on Power Semiconductor Devices and Smart Power IC Technologies

Power semiconductor devices have been a mainstay of electron device technology since the introduction of the thyristor in the late 1950s. In the last six decades, electron devices and VLSI technology have gone through unprecedented changes. The state-of-the-art performance has progressed closely according to the famous Moore's Law, since it was introduced in 1965. The current techno-trend is the “More Than Moore” roadmap with emphasis on System in Package and 3-D integration. Over this period, we have witnessed device feature sizes shrinking from several microns in the 1970s to the 10-nm production-ready processes in 2017. At the same time, power semiconductor devices have also benefited significantly from these advancements.

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a dc–dc buck converter chip fabricated with a 0.35 $\mu\text{m}$ high-voltage-CMOS technology. The dc coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult to implement and to verify during the design of a complex Smart Power circuit. These rules are often based on the physical device simulations or on the empirical results extracted from predefined benchmark structures. In this paper, a novel approach is proposed for designing robust circuits integrating accurate and specific analysis of substrate couplings already into the design flow. First, substrate currents injected by power transistors are discussed to show the spatial distribution of voltage and currents into the substrate. A set of guidelines to optimize substrate currents is presented as a summary of the studied test cases. Then, an H-Bridge output driver was implemented in a $0.35$ - $\mu$ m HVCMOS technology to investigate substrate currents by both measurements and simulations. Reverse currents were deliberately injected into the chip to activate substrate lateral and vertical parasitic bipolar junction transistors and measured data closely match circuit simulation results in both cases.

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

In many automotive applications, repetitive self-heating is the most critical operation condition for LDMOS transistors in smart power ICs. This is attributed to thermo-mechanical stress in the on-chip metallization, which results from the different thermal expansion coefficients of the metal and the intermetal dielectric. After many cycles, the accumulated strain in the metallization can lead to short circuits, thus limiting the lifetime. Increasing the LDMOS size can help to lower peak temperatures and therefore to reduce the stress. The downside of this is a higher cost. Hence, it has been suggested to use resilient systems that monitor the LDMOS metallization and lower the stress once a certain level of degradation is reached. Then, lifetime requirements can be fulfilled without oversizing LDMOS transistors, even though a certain performance loss has to be accepted. For such systems, suitable sensors for metal degradation are required. This work proposes a floating metal line embedded in the LDMOS metallization. The suitability of this approach has been investigated experimentally by test structures and shown to be a promising candidate. The obtained results will be explained by means of numerical thermo-mechanical simulations.

Design and Characterization of a Secondary Side Smart-Power Integrated Active Asynchronous Voltage Clamp

As is well known in the design of transformer isolated converters, the transformer leakage inductance causes a large voltage overshoot on the secondary side switching nodes at every switch transition, unless measures are taken to limit the peak voltage stress. Since the peak voltage stress in smart-power integrated converters, where the power devices are integrated on the same die as the controlling logic and supporting circuits, is the major determining factor for the required silicon area for the implementation, this is a major roadblock for the affordable integration of this type of converter. Therefore, any cost-effective smart-power synchronous rectifier requires a voltage clamping circuit that minimizes the voltage stress, while still maintaining the potential advantages of smart-power converters, i.e. minimizing the number and size of the discrete components in the converter. We present an integrated asynchronous active clamping circuit, that can clamp the overshoot voltage to arbitrary voltages while optimizing the efficiency by only being active when required. Because of the asynchronous operation, the size of the required external components is minimized. Measurements on the smart-power IC implementation of the asynchronous active clamp circuit combined with a secondary side synchronous rectifier for a 1 MHz full bridge converter confirm the reduction in voltage stress and the optimization of the efficiency.

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift–diffusion. In this case the conductivity of the substrate is spatially modulated and this effect is particularly important in high injection regime. In this work a description of the coupling between majority and minority drift–diffusion currents is presented. A distributed model of the substrate is then proposed to take into account the conductivity modulation and its feedback on diffusion processes. The model is expressed in terms of equivalent circuits in order to be fully compatible with circuit simulators. The simulation results are then discussed for diodes and bipolar transistors and compared to the ones obtained from physical device simulations and measurements.

Substrate-Coupled Cross-Talk Effects on an AlGaN/GaN-on-Si Smart Power IC Platform

Cross talks between low-voltage peripheral devices and high-voltage (HV) power devices on an AlGaN/GaN-on-Si smart power IC platform are investigated by monitoring the transfer, output, and transient characteristics of a low-voltage AlGaN/GaN high-electron mobility transistor (HEMT) with an HV bias stress applied to an adjacent isolated electrode. The electric measurement was conducted under two types of substrate termination, i.e., floating and grounded. The substrate termination is shown to be the critical factor in the cross talk. The low-voltage HEMT exhibits significant drain-current degradation with a floating substrate, but remains stable with a grounded substrate. It is determined that a coupling path of the switched HV stress is formed from the HV node to the floating low-resistivity Si substrate, and then from the substrate to the HEMT. The negative net charges in the GaN buffer are caused by the electrons injected from the 2DEG channel. It is found that a grounded substrate is helpful for eliminating the cross-talk effect.

Susceptibility of Smart Power ICs to Radio Frequency Interference

This paper deals with the susceptibility to radio frequency interference (RFI) of the analog front ends embedded in smart power integrated circuits. The case of RFI injected in the power transistor terminals that propagates to the analog front ends of the same integrated circuit is investigated using equivalent circuits that include the silicon substrate. The demodulation of the interference that takes place in the analog front-end circuits is evaluated by means of an approximate nonlinear method. In particular, it is shown that the demodulation of the substrate interference in a MOS differential input stage depends on the asymmetry of the circuits connected to the input terminals. Based on this, a simple method to increase the immunity to such interference is presented and its effectiveness is proved through computer simulations and through measurements carried out on a test chip.

Electro-Thermal Design of Smart Power Devices and Integrated Circuits

An efficient methodology of electro-thermal design of smart power semiconductor devices and ICs, based on the combined use of SPICE circuit analysis tool and software tools for 2D/3D thermal simulation of IC chip construction, is presented. The features of low, medium and high power elements, temperature sensors, IC chips simulation are considered.

Power optimal gate current profiles for the slew rate control of Smart Power ICs

Smart Power ICs are Power Switches with integrated control and protection functions. In order to meet the electromagnetic compatibility requirements, the output terminal slew rate has to be limited during the switching operation. In this context, special feedforward gate current profiles are widely used to control the switching slew rate. These profiles are typically determined on the basis of a linearized mathematical model of the Smart Power IC. However, due to the nonlinear characteristics of the IC, these profiles may lead to a reduced switching speed and thus to higher switching losses. In this work, an optimal control problem is considered which systematically accounts for the nonlinearities of the Power Switch, the switching losses and the limitation of the slew rate. In particular, a tailored mathematical model of the Smart Power IC is developed and parametrized. Based on this, the optimal control problem is formulated, numerically solved and the results are presented.

Fully Integrated High-Voltage Generators with Optimized Power Efficiency

This paper describes how the power efficiency of fully integrated Dickson charge pumps in high- voltage IC technologies can be improved considerably by implementing charge recycling techniques, by replacing the normal PN junction diodes by pulse-driven active diodes, and by choosing an appropriate advanced smart power IC technology. A detailed analysis reveals that the combination of these 3 methods more than doubles the power efficiency compared to traditional Dickson charge pump designs.

A Study on 400V Sized Trench Power Semiconductor for Smart Power ICs

Power MOSFET is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Recently attention to the motor and the application of various technologies. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters, motor controllers. In this paper, design the 400 V Planar type, and design the trench type for realization of low on-resistance. Trench Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

Integrated Over-Temperature Protection Circuit for GaN Smart Power ICs

As a thermal sensing and protection module on a GaN smart power IC platform, the first GaN over-temperature protection (OTP) circuit is demonstrated to deliver a desirable triggering signal at the critical temperature. The integrated OTP circuit is realized based on monolithic integration of enhancement-/depletion-mode high electron mobility transistors (HEMT) and HEMT-compatible lateral field effect rectifiers on a baseline AlGaN/GaN-on-Si wafer. The circuit effectively indicates the over-temperature up to 250 °C, and has a power supply rejection radio well above 35 dB. This sensing/protection circuit is expected to provide enhanced reliability to the high-voltage GaN power devices.

On the Origin of Thermal Runaway in a Trench Power MOSFET

In this paper, we investigate the origin of thermal runaway in the trench power MOSFET of a modern smart power IC technology. Experimental data on the temperature rise during power pulses show that the onset of thermal runaway depends on the biasing condition even if the power pulses have equal power dissipation. The beginning of thermal runaway in this work is denoted by the inflection point in the measured temperature data. For the experimental data points, the onset varies from 340 °C to 520 °C. Comparison of these experimental data with an analysis based on the stability factor shows very good agreement. The stability factor analysis demonstrates that, above the temperature compensation point (TCP), the driving force for thermal runaway is the thermally generated leakage current of the parasitic n-p-n bipolar transistor. The decrease of mobility and, hence, the MOS channel current above the TCP stabilizes the power MOSFET. In contrast, below the TCP, both the increase of the MOS channel current and the parasitic n-p-n bipolar transistor leakage current with temperature contribute to the thermal runaway.

Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.

A Direct Measurement Method of Frequency Responses of the Smart Power IC

Smart power ICs are widely used in universal input power supplies. This paper presents a detailed analysis and scheme design for real-time small-signal modeling method for smart power IC. First, in this method, the switching duty cycle is converted into a voltage output signal based on the operational characteristics of the power IC. The power IC's frequency response is then obtained by measuring the duty cycle output signal and the power IC's control input signal. The modeling system is referred to as sampling the duty cycle of the power IC with a zero-order hold output. Using least-square identification, the smart power IC's dynamic model and transfer function are synthesized from the measurement data. The results of the modeling experiment are discussed, and practical guidelines and error amplifier (EA) design examples are presented for both continuous and discontinuous conduction modes (CCM and DCM). The effectiveness and practicality are verified through experiments.