Small Gate Leakage Research Articles

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Exploration of vertical scaling limit in carbon nanotube transistors

Top-gated carbon nanotube field-effect transistors (CNT FETs) were fabricated by using ultra-thin (4.5 nm or thinner) atomic-layer-deposition grown HfO2 as gate insulator, and shown to exhibit high gate efficiency, i.e., all examined (totally 76) devices present very low room temperature subthreshold swing with an averaged value of 64 mV/Dec, without observable carrier mobility degradation. The gate leakage of the CNT FET under fixed gate voltage is dependent not only on the thickness of HfO2 insulator, but also on the diameter of the CNT. The vertical scaling limit of CNT FETs is determined by gate leakage standard in ultra large scale integrated circuits. HfO2 film with effective oxide thickness of 1.2 nm can provide both excellent gate electrostatic controllability and small gate leakage for sub-5 nm FETs based on CNT with small diameter.

Electrical properties of LaTiO high-k gate dielectric Ge MOS Capacitor and Ti content optimization

Ti is intentionally added into La2O3 to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capacitor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La2O3 ratios (10.6%, 18.4%, 25.7% and 31.5%) are deposited by reactively co-sputtering Ti and La2O3 targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La2O3. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La2O3 ratios in the examined range, the largest Ti/La2O3 ratio is 31.5%, which results in the highest k value of 29.4, the largest gate-leakage current of 9.710-2 Acm-2 at Vg=1 V, the highest interface-sate density of 4.51012 eV-1cm-2 and the worst device reliability, while the La2O3 film without Ti incorporation exhibits the lowest k value of 11.7, the smallest gate-leakage current of 2.510-3 Acm-2 at Vg=1 V, the lowest interface-sate density of 3.31011 eV-1cm-2 and the best device reliability. As far as the trade-off among the electrical properties is concerned, 18.4% is the most suitable Ti/La2O3 ratio, which leads to a higher k value of 22.7, lower interface-sate density of 5.51011 eV-1cm-2, an acceptable gate-leakage current of 7.110-3 Acm-2 at Vg=1 V, and a better device reliability. In view of the fact mentioned above, excellent electrical properties could be obtained by setting Ti content to be an optimal value. Therefore, the optimization of Ti content is critical for LaTi-based oxide Ge MOS device preparation.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 1011 cm−2/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10−6 A/cm2 at Vfb + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-like interface and near-interface traps.

Silicon nanowire biosensors for detection of cardiac troponin I (cTnI) with high sensitivity.

We have demonstrated highly sensitive and label-free detection of cardiac troponin I (cTnI), a biomarker for diagnosis of acute myocardial infarction, using silicon nanowire field-effect transistors. A honeycomb-like structure is utilized for nanowire configuration to offer improved electrical performance and increased sensing area. The fabricated devices show n-type behavior with a relatively high ON-OFF current ratio, small sub-threshold swing and low gate leakage current. Monoclonal antibodies for cTnI were covalently immobilized on the nanowire surface and the attachment of antibodies is clearly visualized by atomic force microscope. The sensitivity with various concentrations of buffer solution was also investigated in order to determine the optimal buffer condition. The devices exhibit highest sensitivity under buffer solutions with low ion concentration. In addition, the detection limit of the sensor is as low as ~5 pg/mL, the lowest reported in the literature to date and nearly an order of magnitude smaller than the suggested threshold limit. The fabricated devices demonstrate a good selectivity for detecting cTnI.

Ultra-low voltage and ultra-low power consumption nonvolatile operation of a three-terminal atomic switch.

Nonvolatile three-terminal operation, with a very small range of bias sweeping (-80 to 250 mV), a high on/off ratio of up to six orders of magnitude, and a very small gate leakage current (<1 pA), is demonstrated using an Ag (gate)/Ta2 O5 (ionic transfer layer)/Pt (source), Pt (drain) three-terminal atomic switch structure.

1/f Noise Characteristics of AlGaN/GaN FinFETs with and without TMAH surface treatment

In this paper, we have fabricated and investigated the AlGaN/GaN fin-shaped field-effect transistors (FinFETs) with and without TMAH surface treatment. DC and noise characteristics of the FinFETs were compared to evaluate the interface quality between Al2O3 layer and the side-wall GaN surface. The tetramethyl ammonium hydroxide (TMAH)-treated device with a fin width of 70nm and gate length, Lg=5μm exhibited excellent device performances, such as drain current of 0.16mA and transconductance (gm) of 0.11ms, both 30% improved, and extremely small gate leakage current of about 10−9A at Vgs=−5V which is approximately two orders lower in magnitude compared to that of the device without TMAH treatment. Improved low-frequency noise performances were obtained for TMAH treated device due to the enhanced side-wall quality after the TMAH surface treatment. The trap density was found to be reduced approximately one order after TMAH treatment. Thus, simple surface treatment not only smoothens the sidewall surface but also eliminates the plasma damage caused during the fin etching, which leads to the reduction of trap density in AlGaN/GaN FinFETs.

MOVPE growth of in situ SiNx/AlN/GaN MISHEMTs with low leakage current and high on/off current ratio

We report the MOVPE growth of high-performance AlN/GaN MISHEMTs using regrown n-type GaN (n-GaN) as source/drain (S/D) and in situ SiNx as gate dielectric. The n-GaN S/D and in situ SiNx were investigated for minimizing on-resistance and suppressing gate leakage current, respectively. The results showed that a two-step Si doping profile for the n-GaN greatly reduced the access resistance, and small gate leakage as well as low trap state density were achieved with the in situ SiNx gate dielectric. The fabricated 0.33μm-gated MISHEMT exhibited a maximum drain current density of 1550mA/mm and an on/off current ratio over 107.

Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG < 20 pA/µm for LG = 10 nm, well below ITRS requirements [3].Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs ~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP , parallel conductance GP circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt and series resistance Rs is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].

Nitrided HfTiON/Ga2O3(Gd2O3) as stacked gate dielectric for GaAs MOS applications

GaAs metal–oxide–semiconductor (MOS) capacitors with HfTiON as a gate dielectric and Ga2O3(Gd2O3) (GGO) as an interlayer annealed in NH3 or N2 are fabricated, and their electrical properties are characterized. Experimental results show that the HfTiON/GGO/GaAs MOS device annealed in NH3 exhibits a low interface-state density (1.1 × 1012 cm−2 eV−1), a small gate leakage current (1.66 × 10−4 A cm−2 at Vg = Vfb + 1 V), a large equivalent dielectric constant (25.7), and a good capacitance–voltage behavior. All these should be attributed to the fact that the GGO interlayer and postdeposition annealing in NH3 can effectively suppress the formation of interfacial Ga/As oxides and remove the excess As atoms at the GaAs surface, thus reducing the relevant defects at/near the GGO/GaAs interface.

Electrical Properties of HfTiON Gate-Dielectric GaAs Metal-Oxide-Semiconductor Capacitor With AlON as Interlayer

High- k HfTiON gate-dielectric GaAs MOS capacitors with and without AlON as interfacial passivation layer (IPL) are fabricated and their interfacial and electrical properties are compared. It is found that low interface-state density ( 1.5×1012 cm-2eV-1 at midgap), small gate leakage current ( 1.3×10-4 A/cm2 at Vg=Vfb+1 V), small capacitance equivalent thickness (1.72 nm), large equivalent dielectric constant (25.6), and high device reliability can be achieved for the Al/HfTiON/AlON/GaAs MOS device. All of these should be due to the fact that the AlON IPL on sulfur-passivated GaAs can effectively reduce the density of defective states and unpin the Femi level at the AlON/GaAs interface, thus greatly improving the interfacial and electrical properties of the device.

Analysis of Failure in Miniature X‐ray Tubes with Gated Carbon Nanotube Field Emitters

We correlate the failure in miniature X‐ray tubes with the field emission gate leakage current of gated carbon nanotube emitters. The miniature X‐ray tube, even with a small gate leakage current, exhibits an induced voltage on the gate electrode by the anode bias voltage, resulting in a very unstable operation and finally a failure. The induced gate voltage is apparently caused by charging at the insulating spacer of the miniature X‐ray tube through the gate leakage current of the field emission. The gate leakage current could be a criterion for the successful fabrication of miniature X‐ray tubes.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm−2 eV−1), small gate leakage current (7.3 × 10−5 A cm−2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene–carbon nanotube transistors

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10(-13) A. The resulting devices exhibited an excellent on/off ratio of ~10(5), a high mobility of ~40 cm(2) V(-1) s(-1) and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

MBE grown Ga2O3 and its power device applications

N-type gallium oxide (Ga2O3) homoepitaxial thick films were grown on β-Ga2O3 (010) substrates by molecular beam epitaxy. The epitaxial growth rate was increased by more than 10 times by changing from the (100) plane to the (010) plane. The carrier concentration of the epitaxial layers could be varied within the range of 1016–1019cm−3 by changing the Sn doping concentration. Schottky barrier diodes (SBDs) and metal–semiconductor field-effect transistors (MESFETs) on β-Ga2O3 homoepitaxial layers were demonstrated for the first time. The SBDs exhibited good device characteristics such as an ideality factor of 1.13, and high breakdown voltage about 125V. The MESFETs also exhibited excellent characteristics such as a perfect pinch-off of the drain current, off-state breakdown voltage over 250V, high on/off drain current ratio of around 104, and small gate leakage current. These device characteristics clearly indicate the great potential of Ga2O3 as a high-power device material.

Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.

Functional Ultrathin Films and Nanolaminates from Aqueous Solutions

Nanolaminates composed of TiO2 and Al4O3(PO4)2 (AlPO) thin films have been fabricated from aqueous solution precursors. By adjusting precursor concentrations individual layers can be controlled to a thickness near 1 nm. Characterization by X-ray reflectivity and transmission electron microscopy (TEM) reveals near-atomically smooth interfaces and a high degree of regularity in the film stacks. X-ray diffraction is utilized to investigate the crystallization behavior of TiO2 layers under one-dimensional confinement of the glassy AlPO layers. TiO2–AlPO nanolaminates incorporated into capacitor structures exhibit low leakage current densities (<10 nA/cm2 at 1 MV/cm) and high breakdown fields up to 5.4 MV/cm with annealing temperatures as low as 350 °C. Tailorable dielectric constants have also been demonstrated by varying the relative thickness of the TiO2 and AlPO films. As gate dielectrics in thin-film transistors with solution-processed amorphous indium gallium zinc oxide channels, the nanolaminates exhibit small gate leakage, enabling ideal transistor performance with incremental mobilities near 3 cm2/V·s.

Effects of TMAH Treatment on Device Performance of Normally Off $\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GaN}$ MOSFET

Normally off Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GaN MOSFETs are fabricated by utilizing a simple tetramethylammonium hydroxide (TMAH) treatment as a postgate-recess process. The TMAH-treated device with a gate length of 2.5 μm exhibited excellent device performances, such as a threshold voltage of 3.5 V, a maximum drain current of 336 mA/mm, and a breakdown voltage of 725 V, along with extremely small gate leakage current of about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> A/mm at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> = 15 V, which is approximately six orders lower in magnitude compared to that of the device without TMAH treatment.

Improved Performance of Yttrium-Doped $\hbox{Al}_{2}\hbox{O}_{3}$ as Inter-Poly Dielectric for Flash-Memory Applications

Yttrium-doped Al2O3 (YxAIyO) with different yttrium contents prepared by co-sputtering method is investigated as the inter-poly dielectric (IPD) for flash memory applications. A poor SiO2-like interlayer formed at the IPD/Si interface is confirmed by X-ray photoelectron spectroscopy, and can be sup pressed by Y doping through the transformation of silica into silicate. Compared with Al2O3 and Y2O3 films, the optimized YxAIyO film shows lower interface-state density, lower bulk charge-trapping density, higher dielectric constant, and smaller gate leakage, due to the suppressed interlayer and good thermal property ascribed to appropriate Y and Al contents in the film. Therefore, the optimized YxAIyO film is a promising candidate as the IPD for flash memory.

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm−2 eV), small gate leakage current (8.6×10−4 A cm−2 at Vg−Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.