Small Chip Size Research Articles

Via-Aware Dogleg Routing Using Boolean Satisfiability

Boolean Satisfiability (SAT)-based channel routing with via-aware pin doglegging is presented in this paper. The effect of the pin dogleg layout of connecting wires has been tested separately for input–output pins and output pins only with controlled use of vias for dogleg during detailed routing. Dogleg may reduce the channel width required for laying down all nets and hence decrease the total chip area. However, invalid selection of dogleg may increase the channel width or may identify a routable circuit as unroutable. Unwanted dogleg may also increase the use of vias (switches) required for changing the track from one to another and may create a congested area with vias. Congested via may introduce lithographic printing problem during manufacturing and power leakage problem. The proposed technique considers all these constraints to provide an optimal result and gives a compact layout for a circuit with controlled via for doglegging. The results obtained show that pin dogleg layout produces a more compact layout for connecting wires with supervised via when compared to dogleg-free routing or doglegged routing with unsupervised via for some standard benchmark circuits. It yields optimal results with reduced number of tracks in a channel and smaller chip size.

A Compact, Active SiGe Power Divider With Multi-Octave Bandwidth

This letter proposes a wideband active power divider, which realizes multi-octave bandwidth with positive, flat gain, and good isolation. By combining a single stage amplifier with artificial transmission lines and emitter-follower (EF) output stages, a broadband operational bandwidth (2.5-23.0 GHz) and flat gain response (8.8-11.8 dB) with a small chip size are achieved while maintaining good isolation ( $>$ 25 dB) between the output ports. The measured noise figures (NFs) of the two forward paths are lower than 9 dB, the output P1dB (OP1dB) is greater than −9 dBm and the output IP3 (OIP3) is greater than 0 dBm over the 3 dB bandwidth. The maximum amplitude and phase imbalances of the two output ports are 0.2 dB and 1.6 degrees, respectively. The core area of the active power divider is $0.62 \times 0.50$ mm $^{{\mathbf {2}}}$ . The active power divider consumes 20 mA from a 3.3 V DC supply.

Design of an Active Inductor-Based T/R Switch in 0.13 μm CMOS Technology for 2.4 GHz RF Transceivers

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm2 that is the lowest-ever reported chip area for this frequency band was achieved.

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma ( $\Delta \Sigma $ ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the $\Sigma \Delta{\rm ADC}$ instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in $0.35 \upmu\hbox{m}$ CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with $35.1 \pm 0.3 \upmu\hbox{V}$ input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being $4 \upmu\hbox{V}/\hbox{e}^-$ . The integration test results show that the readout noise is $11.8 \hbox{e}^ {-} $ at 100 kHz readout pixel rate and the achieved energy spectrum resolution is $168 \hbox{eV} \pm 4.7 \hbox{eV}$ (Full Width at Half Maximum: FWHM) at 5.9 keV.

Effects and contrasts of silicon‐on‐insulator floating‐body and body‐contacted field‐effect transistors to the design of high‐performance antenna switches

A theoretical analysis and contrast of silicon-on-insulator (SOI) floating-body (FB) and body-contacted (BC) metal–oxide–semiconductor field-effect transistors (FETs) including insertion loss (IL), isolation, power handling capability as well as harmonics for radio frequency switches applications, are firstly developed in detail. From the presented investigation, lower IL and smaller chip size can be obtained using FB FETs, while the BC devices are beneficial to isolation and harmonics improvement. As an experimental vehicle for the presented analysis, the high-power single-pole eight-throw (SP8T) antenna switches for multi-mode multi-band applications, are fabricated in a partially depleted 0.18 μm SOI process based on FB and BC FETs, respectively. At 1.9 GHz, the tested IL, TR × 1 to TR × 3 isolation, and P −0.1 dB of the FB and BC SP8T switches are approximately 0.53/0.65 dB, 27.6/29.3 dB and 38.0/38.4 dBm. For the two cases, the second and third harmonics are −70.6/−75.5 and −60.4/−79.9 dBc, respectively, with a +33 dBm input power at 1.9 GHz. The experimental results strongly support the analysis that the FB FET is a preferred device in low loss or low throw-count switching design while the BC FET is a better selection in the applications that demand high power and low harmonic.

Design of a fully integrated receiver analog baseband chain for 2.4-GHz ZigBee applications

A receiver analog baseband (ABB) chain for an integrated ZigBee (IEEE 802.15.4) transceiver is presented in this paper. The ABB is composed by a 3rd-order complex band-pass filter (BPF), a variable gain amplifier (VGA) and an analog-to-digital converter (ADC). The circuit topology of each building block has been designed complying with the IEEE 802.15.4 standard as well as featuring low power consumption and small chip size. In this work, a mixed-signal frequency auto-tuning scheme is proposed for complex BPF to accommodate the performance deterioration due to the process, voltage and temperature (PVT) variations. A novel method combined opamp- and capacitor-sharing is presented for ADC to obtain low power consumption and elimination of memory effect. The proposed ABB demonstrates 70dB dynamic range by 2dB/step, 12dBm IIP3 and 35.2nV/√Hz input referred noise. The measured SNDR and SFDR are 41.9dB and 58.7dB, respectively. Implemented in a standard 0.18-μm CMOS technology, the entire receiver ABB chain occupies an area as small as 1.5mm2 and the total power consumption is only 16mW at max gain setting from a 1.8V supply.

Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology

This brief presents the analysis and design of a two-stage stacked power amplifier (PA) with very broadband gain frequency response and power performance in a small chip size. The broadband load impedance match is realized using modified stacked field-effect transistors (FETs) with a resistive feedback by analyzing the matching condition of the source input impedance of the stacked FET. In order to further improve the broadband gain frequency response, the effectiveness of a gain expansion from a stacked driver amplifier is demonstrated to compensate the gain compression of the last-stage amplifier. To verify the design concept, a two-stage three-stacked PA has been implemented in a 0.18- $\mu\mbox{m}$ CMOS technology. The PA achieves a saturated output power of 22–24.3 dBm and a power added efficiency of 13%–20% within a 194% fractional bandwidth from 0.1 to 6.5 GHz. It also demonstrates better than 11-dB input return loss (RL) and better than 5.1-dB output RL. This PA occupies a chip size of 0.64 mm2 including pads.

Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

VOC Gas Sensors Fabricated with Graphene Oxide Composites for Food Safety and Quality

In this study, an array sensor is investigated to employ graphene oxide (GO) and nanostructured SnO2, and their composite films for agriculture applications. A series of electrodes was fabricated to create a high density of sensing array in a small size chip. Individual films under various mixing ratios of GO and SnO2 were deposited via electrophoretic deposition (EPD). Formaldehyde gas was employed to explore sensing behavior and the concentration was kept to 100 ppm. The composition gradients in sensing layers can provide unique response pattern according to oxide mixture ratio.

A Nanocurrent Power Management IC for Multiple Heterogeneous Energy Harvesting Sources

This paper presents a fully autonomous power converter IC for energy harvesting from multiple and multitype sources, such as piezoelectric, photovoltaic, thermoelectric, and RF transducers. The converter performs an independent self-adapting input power tracking process for each source. The peak power conversion efficiency measured during single-source operation is 89.6%. With all sources enabled, the intrinsic current consumption is as low as 47.9 nA/source. A self-starting battery-less architecture has been implemented in a 0.32-μm STMicroelectronics BCD technology with a 2142 μm × 2142 μm die area. The IC only requires a single-shared inductor and an external storage capacitor for the basic working configuration. With respect to other multisource energy harvesters, this design specifically introduces a series of nanopower design techniques for extreme minimization of the intrinsic consumption during operation. The small chip size combined with the limited number of required external component, the high conversion efficiency, and the state-of-the-art intrinsic nanocurrent consumption make the IC suitable for many critical applications with very limited available power, such as wearable devices or unobtrusive wireless sensor networks.

VOC Gas Sensors Fabricated with Graphene Oxide Composites for Food Safety and Quality

For food market, off-odors or flavors have become more than a quality issue with the increased awareness of food safety problems. This awareness to solve the safety problems, off-odor detection in foods, packaging materials, and their interactions involving scalping or other flavor system modification have been attracted. One of suggested methods is to use an electronic nose consisting of a gas sensor array to detect the volatile organic compounds (VOCs), released from foods as a byproduct of everyday physiological processes. Monitoring of the specific VOCs by a gas sensor can provide the information on both crop and field conditions. The array structure of gas sensors can enhance selectivity for in-situ detection [1, 2]. In this study, an array of sensors is investigated by employing graphene oxide and nanostructured metal oxide based on SnO2. Their composite films on a series of electrodes are prepared to create a high density of sensing array in a small size chip. A composition gradient sensing layers can produce unique gas response patterns. Figure 1 shows surface morphology of compositionally gradient tin oxides (1:6 ratio of GO to SnO2) and structure property confirmed by XRD result. The results on the growth of nanostructured films using solution process and vacuum process are presented. Figure 2 also shows sensing properties of the composites to formaldehyde gas at room temperature. The combinatorial structure enhances the sensing properties of devices in terms of sensitivity, selectivity and response rate. Additionally, such a sensor can meet the proposed idea, in-situ detection, and also the requirements for low-cost and high-volume production as well as high gas analytical performance. This research was partially supported by a grant from a Strategic Research Project (2013-0132) funded by the Korea Institute of Construction Technology, and Auburn University IGP. [1] A. D. Wilson and M. Baietto. Sensors. 2009, 9:5099-5148. [2] K. Arshak, E. Moore, G. M. Lyons, J. Harris, and S. Clifford. Sensor Review. 2004, 24(2):181-198. Figure 1

A 220–285 GHz SPDT Switch in 65-nm CMOS Using Switchable Resonator Concept

The paper reports a single-pole double-throw (SPDT) switch operating from 220 to 285 GHz in 65-nm bulk CMOS. The switchable resonator concept by using three coupled-lines topology is proposed and adopted in the switch design. Equivalent circuit models are introduced for analyzing the operation mechanism of proposed switch. The fabricated SPDT switch features measured insertion loss of 4.2 dB including RF pad losses, isolation of 19 dB, return loss of better than 10 dB, simulated ${\rm P}_{1 {\rm dB}}$ of 9.2 dBm, and zero power consumption. To the best of authors' knowledge, this switch achieves the highest operating frequency and smallest chip size among reported SPDT switches in CMOS and BiCMOS technologies .

Study on loading coefficient in steam explosion process of corn stalk

The object of this work was to evaluate the effect of loading coefficient on steam explosion process and efficacy of corn stalk. Loading coefficient’s relation with loading pattern and material property was first revealed, then its effect on transfer process and pretreatment efficacy of steam explosion was assessed by established models and enzymatic hydrolysis tests, respectively, in order to propose its optimization strategy for improving the process economy. Results showed that loading coefficient was mainly determined by loading pattern, moisture content and chip size. Both compact loading pattern and low moisture content improved the energy efficiency of steam explosion pretreatment and overall sugar yield of pretreated materials, indicating that they are desirable to improve the process economy. Pretreatment of small chip size showed opposite effects in pretreatment energy efficiency and enzymatic hydrolysis performance, thus its optimization should be balanced in investigated aspects according to further techno-economical evaluation.

Low thermal-mass LEDs: size effect and limits.

In this work, low thermal-mass LEDs (LTM-LEDs) were developed and demonstrated in flip-chip configuration, studying both experimentally and theoretically the enhanced electrical and optical characteristics and the limits. LTM-LED chips in 25 × 25 μm2, 50 × 50 μm2, 100 × 100 μm2 and 200 × 200 μm2 mesa sizes were fabricated and comparatively investigated. Here it was revealed that both the electrical and optical properties are improved by the decreasing chip size due to the reduced thermal mass. With a smaller chip size (from 200 μm to 50 μm), the device generally presents higher current density against the bias and higher power density against the current density. However, the 25 × 25 μm2 device behaves differently, limited by the fabrication margin limit of 10 μm. The underneath mechanisms of these observations are uncovered, and furthermore, based on the device model, it is proven that for a specific flip-chip fabrication process, the ideal size for LTM-LEDs with optimal power density performance can be identified.

Optimizing n-type contact design and chip size for high-performance indium gallium nitride/gallium nitride-based thin-film vertical light-emitting diode

The effects of the n-contact design and chip size on the electrical, optical and thermal characteristics of thin-film vertical light-emitting diodes (VLEDs) were investigated to optimize GaN-based LED performance for solid-state lighting applications. For the small (chip size: 1000×1000µm2) and large (1450×1450µm2) VLEDs, the forward bias voltages are decreased from 3.22 to 3.12V at 350mA and from 3.44 to 3.16V at 700 mA, respectively, as the number of n-contact via holes is increased. The small LEDs give maximum output powers of 651.0–675.4mW at a drive current of 350mA, while the large VLEDs show the light output powers in the range 1356.7–1380.2mW, 700mA, With increasing drive current, the small chips go through more severe degradation in the wall-plug efficiency than the large chips. The small chips give the junction temperatures in the range 51.1–57.2°C at 350 mA, while the large chips show the junction temperatures of 83.1–93.0°C at 700 mA, The small LED chips exhibit lower junction temperatures when equipped with more n-contact via holes.

Lower-power, high-linearity class-AB current-mode programmable gain amplifier

A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099 μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.

A CMOS fifth-derivative Gaussian pulse generator for UWB applications

A CMOS fifth-derivative Gaussian pulse generator is presented for ultra-wideband (UWB) applications. The design exhibits low power consumption, low circuit complexity, and a precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The pulse generator is implemented with a 1.8-V, 0.18-μm CMOS process. The small core chip size of the pulse generator is only 217 × 121 μm2 because of its all digital circuit design. The measured fifth-derivative Gaussian pulse has a peak-to-peak amplitude of 158 mV and a pulse width of 800 ps. The average power dissipation is 0.6 mW with a pulse repetition frequency of 50 MHz.

A novel evaporation detection system using an impedance sensing chip.

This paper presents a novel real-time impedance sensing chip for the evaporation detection of small volume solutions. Time sharing detection is performed for multiple sample measurements by a relay switching technique. In contrast to a conventional weight loss approach, the advantage of this proposed impedance sensing system is that it not only merely requires as little as 0.5 mL of test samples, but also provides high sensitivity and fast detection. More importantly, this proposed impedance sensing chip has advantages of a small chip size and easy decomposition for cleaning and reuse.

Invited: Wafer-Bonding for MEMS – Status and Trends

The current sensor portfolio at Bosch is covering a large variety of different MEMS-based sensor products for automotive and consumer applications. Examples for automotive applications are pressure sensors for engine control, side impact detection and inertial sensors for airbag systems, navigation and vehicle-dynamics control (ESP). Examples for consumer applications are inertial sensors for gaming, freefall detection in laptops, switching in mobile-phones and pressure sensors used as altimeter, barometer and indoor navigation. Among the different wafer bonding techniques for wafer-level packaging that are shown in figure 1, anodic bonding, glass-frit and eutectic bonding are state-of the-art for MEMS sensors and the metallic bonding processes thermo-compression and solid-liquid interdiffusion (SLID) bonding have a high potential for future applications.The basic features that wafer bonding technologies for MEMS must fulfil for a successful wafer-level packaging process are hermeticity, high bond strength and high temperature stability. Glass-frit and anodic bonding are well and long-term established standard technologies used for hermetic packaging of MEMS on wafer-level. But both technologies require comparatively large chip sizes that are not compatible with the requirements for miniaturization and cost reduction of new consumer sensors. Therefore metallic bonding processes like eutectic bonding with aluminium-germanium were used for new consumer sensors. Typically, the bond frame size with the eutectic bond can be reduced by a factor of 2 in combination with a frame that stops the liquid eutectic material in lateral extent. With eutectic bonding very small chip sizes are possible resulting in shrinking the size of Bosch accelerometers as shown in figure 2. One step further is the realization of hermetic encapsulation and electrical interconnection, if an ASIC wafer serves as a functionalized cap. Cu-Cu thermo-compression and Cu / Sn SLID bonding are promising techniques that are of high interest for MEMS products of the future.The wafer bonding processes used and under development at Bosch, examples, advantages, disadvantages and challenges will be described.Figure 1: Overview of waferbonding technologies.Figure 2: Shrinking the chip-size for smaller accelerometers was promoted by the change from glass-frit to eutectic wafer bonding.

Design and implementation of intrabody communication hub/alarm unit in IBC platform for fall prevention system

ABSTRACTWe report a high‐performance intrabody communication (IBC) hub/alarm unit in IBC platform for fall prevention system. The IBC hub/alarm unit consists of a binary frequency shift keying (BFSK) receiver, an on–off keying (OOK) transmitter, an audio digital‐to‐analog converter (DAC), an audio power amplifier (PA), and a microcontrol unit (MCU). The BFSK receiver receives the biomedical signals from the IBC sensor node biomedical system‐on‐a‐chips (SOC) through human body, and then transmits them to PDA/cell phone or earphone alarm terminal through the MCU. The OOK transmitter takes commands from PDA/cell phone, and then transmits them to the IBC sensor node biomedical SOC through human body. The audio DAC and PA send an alarm message to the earphone in case of anomaly based on the biomedical signals received by the BFSK receiver. Such kind of transmission methodology in conjunction with our proposed IBC platform is much more power‐efficient than wireless communication. Moreover, since no antenna is required, small chip size is achieved. At supply voltage of 0.7 V, the BFSK receiver consumes 520 µW (0.17 nJ/b) and achieves sensitivity of −80 dBm at data rate of 3 Mbps, better than previous work in the literature. The excellent results indicate the IBC hub/alarm unit is suitable for IBC platform for fall prevention system. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2345–2351, 2014